mirror of
https://github.com/torvalds/linux.git
synced 2024-12-14 23:25:54 +00:00
d6dd735f4b
Because the CPU1 start address is different for socfpga-vt and socfpga-cyclone5, we add code to use the correct CPU1 start addr. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Signed-off-by: Pavel Machek <pavel@denx.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Olof Johansson <olof@lixom.net>
34 lines
863 B
ArmAsm
34 lines
863 B
ArmAsm
/*
|
|
* Copyright (c) 2003 ARM Limited
|
|
* Copyright (c) u-boot contributors
|
|
* Copyright (c) 2012 Pavel Machek <pavel@denx.de>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#include <linux/linkage.h>
|
|
#include <linux/init.h>
|
|
|
|
__CPUINIT
|
|
.arch armv7-a
|
|
|
|
ENTRY(secondary_trampoline)
|
|
movw r2, #:lower16:cpu1start_addr
|
|
movt r2, #:upper16:cpu1start_addr
|
|
|
|
/* The socfpga VT cannot handle a 0xC0000000 page offset when loading
|
|
the cpu1start_addr, we bit clear it. Tested on HW and VT. */
|
|
bic r2, r2, #0x40000000
|
|
|
|
ldr r0, [r2]
|
|
ldr r1, [r0]
|
|
bx r1
|
|
|
|
ENTRY(secondary_trampoline_end)
|
|
|
|
ENTRY(socfpga_secondary_startup)
|
|
bl v7_invalidate_l1
|
|
b secondary_startup
|
|
ENDPROC(socfpga_secondary_startup)
|