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a8de5ce989
Spelling fixes in arch/ppc/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: Paul Mackerras <paulus@samba.org>
126 lines
2.5 KiB
C
126 lines
2.5 KiB
C
/*
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*
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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*
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* Module name: ppc403_pic.c
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*
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* Description:
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* Interrupt controller driver for PowerPC 403-based processors.
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*/
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/*
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* The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
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* 32 possible interrupts, a majority of which are not implemented on
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* all cores. There are six configurable, external interrupt pins and
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* there are eight internal interrupts for the on-chip serial port
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* (SPU), DMA controller, and JTAG controller.
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*
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/stddef.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/irq.h>
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#include <asm/ppc4xx_pic.h>
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#include <asm/machdep.h>
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/* Function Prototypes */
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static void ppc403_aic_enable(unsigned int irq);
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static void ppc403_aic_disable(unsigned int irq);
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static void ppc403_aic_disable_and_ack(unsigned int irq);
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static struct hw_interrupt_type ppc403_aic = {
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.typename = "403GC AIC",
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.enable = ppc403_aic_enable,
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.disable = ppc403_aic_disable,
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.ack = ppc403_aic_disable_and_ack,
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};
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int
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ppc403_pic_get_irq(void)
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{
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int irq;
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unsigned long bits;
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/*
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* Only report the status of those interrupts that are actually
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* enabled.
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*/
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bits = mfdcr(DCRN_EXISR) & mfdcr(DCRN_EXIER);
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/*
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* Walk through the interrupts from highest priority to lowest, and
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* report the first pending interrupt found.
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* We want PPC, not C bit numbering, so just subtract the ffs()
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* result from 32.
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*/
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irq = 32 - ffs(bits);
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if (irq == NR_AIC_IRQS)
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irq = -1;
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return (irq);
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}
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static void
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ppc403_aic_enable(unsigned int irq)
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{
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int bit, word;
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bit = irq & 0x1f;
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word = irq >> 5;
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ppc_cached_irq_mask[word] |= (1 << (31 - bit));
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mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
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}
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static void
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ppc403_aic_disable(unsigned int irq)
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{
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int bit, word;
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bit = irq & 0x1f;
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word = irq >> 5;
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ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
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mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
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}
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static void
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ppc403_aic_disable_and_ack(unsigned int irq)
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{
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int bit, word;
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bit = irq & 0x1f;
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word = irq >> 5;
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ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
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mtdcr(DCRN_EXIER, ppc_cached_irq_mask[word]);
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mtdcr(DCRN_EXISR, (1 << (31 - bit)));
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}
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void __init
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ppc4xx_pic_init(void)
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{
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int i;
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/*
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* Disable all external interrupts until they are
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* explicitly requested.
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*/
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ppc_cached_irq_mask[0] = 0;
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mtdcr(DCRN_EXIER, ppc_cached_irq_mask[0]);
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ppc_md.get_irq = ppc403_pic_get_irq;
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for (i = 0; i < NR_IRQS; i++)
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irq_desc[i].chip = &ppc403_aic;
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}
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