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The property "pl022,com-mode" can only assume one of the values of the enum ssp_mode, defined in include/linux/amba/pl022.h List the possible numeric values and report the associated meaning. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
71 lines
2.3 KiB
Plaintext
71 lines
2.3 KiB
Plaintext
ARM PL022 SPI controller
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Required properties:
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- compatible : "arm,pl022", "arm,primecell"
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- reg : Offset and length of the register set for the device
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- interrupts : Should contain SPI controller interrupt
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- num-cs : total number of chipselects
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Optional properties:
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- cs-gpios : should specify GPIOs used for chipselects.
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The gpios will be referred to as reg = <index> in the SPI child nodes.
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If unspecified, a single SPI device without a chip select can be used.
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- pl022,autosuspend-delay : delay in ms following transfer completion before
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the runtime power management system suspends the
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device. A setting of 0 indicates no delay and the
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device will be suspended immediately
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- pl022,rt : indicates the controller should run the message pump with realtime
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priority to minimise the transfer latency on the bus (boolean)
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- dmas : Two or more DMA channel specifiers following the convention outlined
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in bindings/dma/dma.txt
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- dma-names: Names for the dma channels, if present. There must be at
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least one channel named "tx" for transmit and named "rx" for
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receive.
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SPI slave nodes must be children of the SPI master node and can
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contain the following properties.
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- pl022,interface : interface type:
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0: SPI
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1: Texas Instruments Synchronous Serial Frame Format
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2: Microwire (Half Duplex)
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- pl022,com-mode : specifies the transfer mode:
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0: interrupt mode
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1: polling mode (default mode if property not present)
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2: DMA mode
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- pl022,rx-level-trig : Rx FIFO watermark level
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- pl022,tx-level-trig : Tx FIFO watermark level
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- pl022,ctrl-len : Microwire interface: Control length
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- pl022,wait-state : Microwire interface: Wait state
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- pl022,duplex : Microwire interface: Full/Half duplex
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Example:
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spi@e0100000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0xe0100000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 31 0x4>;
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dmas = <&dma-controller 23 1>,
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<&dma-controller 24 0>;
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dma-names = "rx", "tx";
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m25p80@1 {
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compatible = "st,m25p80";
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reg = <1>;
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spi-max-frequency = <12000000>;
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spi-cpol;
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spi-cpha;
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pl022,interface = <0>;
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pl022,com-mode = <0x2>;
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pl022,rx-level-trig = <0>;
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pl022,tx-level-trig = <0>;
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pl022,ctrl-len = <0x11>;
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pl022,wait-state = <0>;
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pl022,duplex = <0>;
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};
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};
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