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a788414796
Update the compatbile string to support Meson-AXG SoCs. Signed-off-by: Sunny Luo <sunny.luo@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
56 lines
1.7 KiB
Plaintext
56 lines
1.7 KiB
Plaintext
Amlogic Meson SPI controllers
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* SPIFC (SPI Flash Controller)
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The Meson SPIFC is a controller optimized for communication with SPI
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NOR memories, without DMA support and a 64-byte unified transmit /
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receive buffer.
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Required properties:
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- compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc"
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- reg: physical base address and length of the controller registers
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- clocks: phandle of the input clock for the baud rate generator
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- #address-cells: should be 1
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- #size-cells: should be 0
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spi@c1108c80 {
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compatible = "amlogic,meson6-spifc";
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reg = <0xc1108c80 0x80>;
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clocks = <&clk81>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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* SPICC (SPI Communication Controller)
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The Meson SPICC is generic SPI controller for general purpose Full-Duplex
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communications with dedicated 16 words RX/TX PIO FIFOs.
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Required properties:
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- compatible: should be:
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"amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs.
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"amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs
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- reg: physical base address and length of the controller registers
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- interrupts: The interrupt specifier
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- clock-names: Must contain "core"
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- clocks: phandle of the input clock for the baud rate generator
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- #address-cells: should be 1
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- #size-cells: should be 0
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Optional properties:
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- resets: phandle of the internal reset line
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See ../spi/spi-bus.txt for more details on SPI bus master and slave devices
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required and optional properties.
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Example :
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spi@c1108d80 {
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compatible = "amlogic,meson-gx-spicc";
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reg = <0xc1108d80 0x80>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core";
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clocks = <&clk81>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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