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https://github.com/torvalds/linux.git
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e85e335f8f
MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
way 6:
Way 6 (512 MB)
Vaddr Paddr ASID Attr RWX Cache
---------- ---------- ---- ---- --- -------
0x00000000 0x00000000 0x01 0x03 RWX Bypass
0x20000000 0x20000000 0x01 0x03 RWX Bypass
0x40000000 0x40000000 0x01 0x03 RWX Bypass
0x60000000 0x60000000 0x01 0x03 RWX Bypass
0x80000000 0x80000000 0x01 0x03 RWX Bypass
0xa0000000 0xa0000000 0x01 0x03 RWX Bypass
0xc0000000 0xc0000000 0x01 0x03 RWX Bypass
0xe0000000 0xe0000000 0x01 0x03 RWX Bypass
This patch adds remapping code at the reset vector or at the kernel
_start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
reconfigures MMUv3 as MMUv2:
Way 5 (128 MB)
Vaddr Paddr ASID Attr RWX Cache
---------- ---------- ---- ---- --- -------
0xd0000000 0x00000000 0x01 0x07 RWX WB
0xd8000000 0x00000000 0x01 0x03 RWX Bypass
Way 6 (256 MB)
Vaddr Paddr ASID Attr RWX Cache
---------- ---------- ---- ---- --- -------
0xe0000000 0xf0000000 0x01 0x07 RWX WB
0xf0000000 0xf0000000 0x01 0x03 RWX Bypass
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
345 lines
8.9 KiB
ArmAsm
345 lines
8.9 KiB
ArmAsm
/*
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* arch/xtensa/kernel/vmlinux.lds.S
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*
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* Xtensa linker script
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2008 Tensilica Inc.
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*
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
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* Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
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*/
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#include <asm-generic/vmlinux.lds.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#include <asm/vectors.h>
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#include <variant/core.h>
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#include <platform/hardware.h>
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OUTPUT_ARCH(xtensa)
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ENTRY(_start)
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#ifdef __XTENSA_EB__
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jiffies = jiffies_64 + 4;
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#else
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jiffies = jiffies_64;
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#endif
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#ifndef KERNELOFFSET
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#define KERNELOFFSET 0xd0003000
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#endif
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/* Note: In the following macros, it would be nice to specify only the
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vector name and section kind and construct "sym" and "section" using
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CPP concatenation, but that does not work reliably. Concatenating a
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string with "." produces an invalid token. CPP will not print a
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warning because it thinks this is an assembly file, but it leaves
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them as multiple tokens and there may or may not be whitespace
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between them. */
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/* Macro for a relocation entry */
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#define RELOCATE_ENTRY(sym, section) \
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LONG(sym ## _start); \
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LONG(sym ## _end); \
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LONG(LOADADDR(section))
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/* Macro to define a section for a vector.
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*
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* Use of the MIN function catches the types of errors illustrated in
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* the following example:
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*
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* Assume the section .DoubleExceptionVector.literal is completely
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* full. Then a programmer adds code to .DoubleExceptionVector.text
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* that produces another literal. The final literal position will
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* overlay onto the first word of the adjacent code section
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* .DoubleExceptionVector.text. (In practice, the literals will
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* overwrite the code, and the first few instructions will be
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* garbage.)
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*/
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#define SECTION_VECTOR(sym, section, addr, max_prevsec_size, prevsec) \
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section addr : AT((MIN(LOADADDR(prevsec) + max_prevsec_size, \
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LOADADDR(prevsec) + SIZEOF(prevsec)) + 3) & ~ 3) \
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{ \
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. = ALIGN(4); \
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sym ## _start = ABSOLUTE(.); \
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*(section) \
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sym ## _end = ABSOLUTE(.); \
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}
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/*
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* Mapping of input sections to output sections when linking.
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*/
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SECTIONS
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{
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. = KERNELOFFSET;
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/* .text section */
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_text = .;
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_stext = .;
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.text :
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{
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/* The HEAD_TEXT section must be the first section! */
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HEAD_TEXT
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TEXT_TEXT
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VMLINUX_SYMBOL(__sched_text_start) = .;
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*(.sched.literal .sched.text)
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VMLINUX_SYMBOL(__sched_text_end) = .;
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VMLINUX_SYMBOL(__lock_text_start) = .;
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*(.spinlock.literal .spinlock.text)
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VMLINUX_SYMBOL(__lock_text_end) = .;
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}
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_etext = .;
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PROVIDE (etext = .);
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. = ALIGN(16);
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RODATA
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/* Relocation table */
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.fixup : { *(.fixup) }
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EXCEPTION_TABLE(16)
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/* Data section */
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_sdata = .;
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RW_DATA_SECTION(XCHAL_ICACHE_LINESIZE, PAGE_SIZE, THREAD_SIZE)
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_edata = .;
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/* Initialization code and data: */
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. = ALIGN(PAGE_SIZE);
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__init_begin = .;
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INIT_TEXT_SECTION(PAGE_SIZE)
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.init.data :
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{
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INIT_DATA
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. = ALIGN(0x4);
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__tagtable_begin = .;
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*(.taglist)
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__tagtable_end = .;
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. = ALIGN(16);
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__boot_reloc_table_start = ABSOLUTE(.);
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RELOCATE_ENTRY(_WindowVectors_text,
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.WindowVectors.text);
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#if XCHAL_EXCM_LEVEL >= 2
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RELOCATE_ENTRY(_Level2InterruptVector_text,
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.Level2InterruptVector.text);
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#endif
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#if XCHAL_EXCM_LEVEL >= 3
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RELOCATE_ENTRY(_Level3InterruptVector_text,
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.Level3InterruptVector.text);
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
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RELOCATE_ENTRY(_Level4InterruptVector_text,
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.Level4InterruptVector.text);
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#endif
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#if XCHAL_EXCM_LEVEL >= 5
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RELOCATE_ENTRY(_Level5InterruptVector_text,
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.Level5InterruptVector.text);
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#endif
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#if XCHAL_EXCM_LEVEL >= 6
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RELOCATE_ENTRY(_Level6InterruptVector_text,
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.Level6InterruptVector.text);
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#endif
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RELOCATE_ENTRY(_KernelExceptionVector_text,
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.KernelExceptionVector.text);
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RELOCATE_ENTRY(_UserExceptionVector_text,
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.UserExceptionVector.text);
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RELOCATE_ENTRY(_DoubleExceptionVector_literal,
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.DoubleExceptionVector.literal);
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RELOCATE_ENTRY(_DoubleExceptionVector_text,
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.DoubleExceptionVector.text);
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RELOCATE_ENTRY(_DebugInterruptVector_text,
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.DebugInterruptVector.text);
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__boot_reloc_table_end = ABSOLUTE(.) ;
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INIT_SETUP(XCHAL_ICACHE_LINESIZE)
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INIT_CALLS
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CON_INITCALL
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SECURITY_INITCALL
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INIT_RAM_FS
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}
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PERCPU_SECTION(XCHAL_ICACHE_LINESIZE)
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/* We need this dummy segment here */
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. = ALIGN(4);
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.dummy : { LONG(0) }
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/* The vectors are relocated to the real position at startup time */
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SECTION_VECTOR (_WindowVectors_text,
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.WindowVectors.text,
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WINDOW_VECTORS_VADDR, 4,
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.dummy)
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SECTION_VECTOR (_DebugInterruptVector_literal,
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.DebugInterruptVector.literal,
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DEBUG_VECTOR_VADDR - 4,
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SIZEOF(.WindowVectors.text),
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.WindowVectors.text)
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SECTION_VECTOR (_DebugInterruptVector_text,
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.DebugInterruptVector.text,
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DEBUG_VECTOR_VADDR,
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4,
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.DebugInterruptVector.literal)
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#undef LAST
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#define LAST .DebugInterruptVector.text
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#if XCHAL_EXCM_LEVEL >= 2
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SECTION_VECTOR (_Level2InterruptVector_text,
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.Level2InterruptVector.text,
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INTLEVEL2_VECTOR_VADDR,
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SIZEOF(LAST), LAST)
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# undef LAST
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# define LAST .Level2InterruptVector.text
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#endif
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#if XCHAL_EXCM_LEVEL >= 3
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SECTION_VECTOR (_Level3InterruptVector_text,
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.Level3InterruptVector.text,
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INTLEVEL3_VECTOR_VADDR,
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SIZEOF(LAST), LAST)
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# undef LAST
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# define LAST .Level3InterruptVector.text
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#endif
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#if XCHAL_EXCM_LEVEL >= 4
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SECTION_VECTOR (_Level4InterruptVector_text,
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.Level4InterruptVector.text,
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INTLEVEL4_VECTOR_VADDR,
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SIZEOF(LAST), LAST)
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# undef LAST
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# define LAST .Level4InterruptVector.text
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#endif
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#if XCHAL_EXCM_LEVEL >= 5
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SECTION_VECTOR (_Level5InterruptVector_text,
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.Level5InterruptVector.text,
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INTLEVEL5_VECTOR_VADDR,
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SIZEOF(LAST), LAST)
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# undef LAST
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# define LAST .Level5InterruptVector.text
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#endif
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#if XCHAL_EXCM_LEVEL >= 6
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SECTION_VECTOR (_Level6InterruptVector_text,
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.Level6InterruptVector.text,
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INTLEVEL6_VECTOR_VADDR,
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SIZEOF(LAST), LAST)
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# undef LAST
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# define LAST .Level6InterruptVector.text
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#endif
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SECTION_VECTOR (_KernelExceptionVector_literal,
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.KernelExceptionVector.literal,
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KERNEL_VECTOR_VADDR - 4,
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SIZEOF(LAST), LAST)
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#undef LAST
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SECTION_VECTOR (_KernelExceptionVector_text,
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.KernelExceptionVector.text,
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KERNEL_VECTOR_VADDR,
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4,
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.KernelExceptionVector.literal)
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SECTION_VECTOR (_UserExceptionVector_literal,
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.UserExceptionVector.literal,
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USER_VECTOR_VADDR - 4,
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SIZEOF(.KernelExceptionVector.text),
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.KernelExceptionVector.text)
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SECTION_VECTOR (_UserExceptionVector_text,
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.UserExceptionVector.text,
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USER_VECTOR_VADDR,
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4,
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.UserExceptionVector.literal)
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SECTION_VECTOR (_DoubleExceptionVector_literal,
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.DoubleExceptionVector.literal,
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DOUBLEEXC_VECTOR_VADDR - 16,
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SIZEOF(.UserExceptionVector.text),
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.UserExceptionVector.text)
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SECTION_VECTOR (_DoubleExceptionVector_text,
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.DoubleExceptionVector.text,
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DOUBLEEXC_VECTOR_VADDR,
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32,
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.DoubleExceptionVector.literal)
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. = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3;
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. = ALIGN(PAGE_SIZE);
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__init_end = .;
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BSS_SECTION(0, 8192, 0)
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_end = .;
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/* only used by the boot loader */
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. = ALIGN(0x10);
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.bootstrap : { *(.bootstrap.literal .bootstrap.text .bootstrap.data) }
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.ResetVector.text RESET_VECTOR_VADDR :
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{
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*(.ResetVector.text)
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}
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/*
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* This is a remapped copy of the Secondary Reset Vector Code.
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* It keeps gdb in sync with the PC after switching
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* to the temporary mapping used while setting up
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* the V2 MMU mappings for Linux.
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*
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* Only debug information about this section is put in the kernel image.
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*/
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.SecondaryResetVector.remapped_text 0x46000000 (INFO):
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{
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*(.SecondaryResetVector.remapped_text)
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}
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.xt.lit : { *(.xt.lit) }
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.xt.prop : { *(.xt.prop) }
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.debug 0 : { *(.debug) }
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.line 0 : { *(.line) }
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.debug_srcinfo 0 : { *(.debug_srcinfo) }
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.debug_sfnames 0 : { *(.debug_sfnames) }
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.debug_aranges 0 : { *(.debug_aranges) }
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.debug_pubnames 0 : { *(.debug_pubnames) }
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.debug_info 0 : { *(.debug_info) }
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.debug_abbrev 0 : { *(.debug_abbrev) }
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.debug_line 0 : { *(.debug_line) }
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.debug_frame 0 : { *(.debug_frame) }
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.debug_str 0 : { *(.debug_str) }
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.debug_loc 0 : { *(.debug_loc) }
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.debug_macinfo 0 : { *(.debug_macinfo) }
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.debug_weaknames 0 : { *(.debug_weaknames) }
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.debug_funcnames 0 : { *(.debug_funcnames) }
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.debug_typenames 0 : { *(.debug_typenames) }
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.debug_varnames 0 : { *(.debug_varnames) }
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.xt.insn 0 :
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{
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*(.xt.insn)
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*(.gnu.linkonce.x*)
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}
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.xt.lit 0 :
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{
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*(.xt.lit)
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*(.gnu.linkonce.p*)
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}
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/* Sections to be discarded */
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DISCARDS
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/DISCARD/ : { *(.exit.literal) }
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}
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