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6bb40dd13b
Rework the interface handling. Delete the interface structure and replace it with a per-interface structure. This changes the way rt2x00 handles the active interface drastically. Copy ieee80211_bss_conf to the this rt2x00_intf structure during the bss_info_changed() callback function. This will allow us to reference it later, and removes the requirement for the device flag SHORT_PREAMBLE flag which is interface specific. Drivers receive the option to give the maximum number of virtual interfaces the device can handle. Virtual interface support: rt2400pci: 1 sta or 1 ap, * monitor interfaces rt2500pci: 1 sta or 1 ap, * monitor interfaces rt2500usb: 1 sta or 1 ap, * monitor interfaces rt61pci: 1 sta or 4 ap, * monitor interfaces rt73usb: 1 sta or 4 ap, * monitor interfaces At the moment none of the drivers support AP and STA interfaces simultaneously, this is a hardware limitation so future support will be very unlikely. Each interface structure receives its dedicated beacon entry, with this we can easily work with beaconing while multiple master mode interfaces are currently active. The configuration handlers for the MAC, BSSID and type are often called together since they all belong to the interface configuration. Merge the 3 configuration calls and cleanup the API between rt2x00lib and the drivers. While we are cleaning up the interface configuration anyway, we might as well clean up the configuration handler as well. Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
811 lines
19 KiB
C
811 lines
19 KiB
C
/*
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Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the
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Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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Module: rt2500usb
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Abstract: Data structures and registers for the rt2500usb module.
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Supported chipsets: RT2570.
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*/
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#ifndef RT2500USB_H
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#define RT2500USB_H
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/*
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* RF chip defines.
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*/
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#define RF2522 0x0000
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#define RF2523 0x0001
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#define RF2524 0x0002
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#define RF2525 0x0003
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#define RF2525E 0x0005
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#define RF5222 0x0010
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/*
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* RT2570 version
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*/
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#define RT2570_VERSION_B 2
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#define RT2570_VERSION_C 3
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#define RT2570_VERSION_D 4
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/*
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* Signal information.
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* Defaul offset is required for RSSI <-> dBm conversion.
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*/
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#define MAX_SIGNAL 100
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#define MAX_RX_SSI -1
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#define DEFAULT_RSSI_OFFSET 120
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/*
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* Register layout information.
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*/
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#define CSR_REG_BASE 0x0400
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#define CSR_REG_SIZE 0x0100
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#define EEPROM_BASE 0x0000
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#define EEPROM_SIZE 0x006a
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#define BBP_SIZE 0x0060
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#define RF_SIZE 0x0014
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/*
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* Control/Status Registers(CSR).
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* Some values are set in TU, whereas 1 TU == 1024 us.
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*/
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/*
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* MAC_CSR0: ASIC revision number.
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*/
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#define MAC_CSR0 0x0400
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/*
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* MAC_CSR1: System control.
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* SOFT_RESET: Software reset, 1: reset, 0: normal.
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* BBP_RESET: Hardware reset, 1: reset, 0, release.
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* HOST_READY: Host ready after initialization.
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*/
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#define MAC_CSR1 0x0402
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#define MAC_CSR1_SOFT_RESET FIELD16(0x00000001)
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#define MAC_CSR1_BBP_RESET FIELD16(0x00000002)
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#define MAC_CSR1_HOST_READY FIELD16(0x00000004)
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/*
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* MAC_CSR2: STA MAC register 0.
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*/
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#define MAC_CSR2 0x0404
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#define MAC_CSR2_BYTE0 FIELD16(0x00ff)
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#define MAC_CSR2_BYTE1 FIELD16(0xff00)
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/*
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* MAC_CSR3: STA MAC register 1.
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*/
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#define MAC_CSR3 0x0406
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#define MAC_CSR3_BYTE2 FIELD16(0x00ff)
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#define MAC_CSR3_BYTE3 FIELD16(0xff00)
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/*
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* MAC_CSR4: STA MAC register 2.
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*/
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#define MAC_CSR4 0X0408
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#define MAC_CSR4_BYTE4 FIELD16(0x00ff)
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#define MAC_CSR4_BYTE5 FIELD16(0xff00)
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/*
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* MAC_CSR5: BSSID register 0.
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*/
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#define MAC_CSR5 0x040a
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#define MAC_CSR5_BYTE0 FIELD16(0x00ff)
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#define MAC_CSR5_BYTE1 FIELD16(0xff00)
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/*
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* MAC_CSR6: BSSID register 1.
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*/
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#define MAC_CSR6 0x040c
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#define MAC_CSR6_BYTE2 FIELD16(0x00ff)
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#define MAC_CSR6_BYTE3 FIELD16(0xff00)
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/*
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* MAC_CSR7: BSSID register 2.
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*/
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#define MAC_CSR7 0x040e
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#define MAC_CSR7_BYTE4 FIELD16(0x00ff)
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#define MAC_CSR7_BYTE5 FIELD16(0xff00)
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/*
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* MAC_CSR8: Max frame length.
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*/
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#define MAC_CSR8 0x0410
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#define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
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/*
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* Misc MAC_CSR registers.
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* MAC_CSR9: Timer control.
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* MAC_CSR10: Slot time.
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* MAC_CSR11: IFS.
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* MAC_CSR12: EIFS.
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* MAC_CSR13: Power mode0.
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* MAC_CSR14: Power mode1.
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* MAC_CSR15: Power saving transition0
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* MAC_CSR16: Power saving transition1
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*/
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#define MAC_CSR9 0x0412
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#define MAC_CSR10 0x0414
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#define MAC_CSR11 0x0416
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#define MAC_CSR12 0x0418
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#define MAC_CSR13 0x041a
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#define MAC_CSR14 0x041c
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#define MAC_CSR15 0x041e
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#define MAC_CSR16 0x0420
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/*
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* MAC_CSR17: Manual power control / status register.
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* Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
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* SET_STATE: Set state. Write 1 to trigger, self cleared.
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* BBP_DESIRE_STATE: BBP desired state.
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* RF_DESIRE_STATE: RF desired state.
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* BBP_CURRENT_STATE: BBP current state.
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* RF_CURRENT_STATE: RF current state.
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* PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
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*/
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#define MAC_CSR17 0x0422
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#define MAC_CSR17_SET_STATE FIELD16(0x0001)
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#define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
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#define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
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#define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
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#define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
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#define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
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/*
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* MAC_CSR18: Wakeup timer register.
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* DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
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* BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
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* AUTO_WAKE: Enable auto wakeup / sleep mechanism.
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*/
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#define MAC_CSR18 0x0424
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#define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
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#define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
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#define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
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/*
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* MAC_CSR19: GPIO control register.
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*/
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#define MAC_CSR19 0x0426
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/*
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* MAC_CSR20: LED control register.
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* ACTIVITY: 0: idle, 1: active.
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* LINK: 0: linkoff, 1: linkup.
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* ACTIVITY_POLARITY: 0: active low, 1: active high.
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*/
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#define MAC_CSR20 0x0428
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#define MAC_CSR20_ACTIVITY FIELD16(0x0001)
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#define MAC_CSR20_LINK FIELD16(0x0002)
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#define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
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/*
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* MAC_CSR21: LED control register.
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* ON_PERIOD: On period, default 70ms.
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* OFF_PERIOD: Off period, default 30ms.
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*/
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#define MAC_CSR21 0x042a
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#define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
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#define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
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/*
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* Collision window control register.
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*/
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#define MAC_CSR22 0x042c
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/*
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* Transmit related CSRs.
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* Some values are set in TU, whereas 1 TU == 1024 us.
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*/
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/*
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* TXRX_CSR0: Security control register.
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*/
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#define TXRX_CSR0 0x0440
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#define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
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#define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
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#define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
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/*
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* TXRX_CSR1: TX configuration.
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* ACK_TIMEOUT: ACK Timeout in unit of 1-us.
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* TSF_OFFSET: TSF offset in MAC header.
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* AUTO_SEQUENCE: Let ASIC control frame sequence number.
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*/
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#define TXRX_CSR1 0x0442
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#define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
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#define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
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#define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
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/*
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* TXRX_CSR2: RX control.
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* DISABLE_RX: Disable rx engine.
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* DROP_CRC: Drop crc error.
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* DROP_PHYSICAL: Drop physical error.
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* DROP_CONTROL: Drop control frame.
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* DROP_NOT_TO_ME: Drop not to me unicast frame.
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* DROP_TODS: Drop frame tods bit is true.
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* DROP_VERSION_ERROR: Drop version error frame.
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* DROP_MCAST: Drop multicast frames.
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* DROP_BCAST: Drop broadcast frames.
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*/
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#define TXRX_CSR2 0x0444
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#define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
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#define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
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#define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
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#define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
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#define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
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#define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
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#define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
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#define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200)
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#define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400)
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/*
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* RX BBP ID registers
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* TXRX_CSR3: CCK RX BBP ID.
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* TXRX_CSR4: OFDM RX BBP ID.
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*/
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#define TXRX_CSR3 0x0446
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#define TXRX_CSR4 0x0448
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/*
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* TXRX_CSR5: CCK TX BBP ID0.
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*/
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#define TXRX_CSR5 0x044a
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#define TXRX_CSR5_BBP_ID0 FIELD16(0x007f)
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#define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080)
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#define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00)
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#define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000)
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/*
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* TXRX_CSR6: CCK TX BBP ID1.
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*/
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#define TXRX_CSR6 0x044c
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#define TXRX_CSR6_BBP_ID0 FIELD16(0x007f)
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#define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080)
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#define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00)
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#define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000)
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/*
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* TXRX_CSR7: OFDM TX BBP ID0.
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*/
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#define TXRX_CSR7 0x044e
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#define TXRX_CSR7_BBP_ID0 FIELD16(0x007f)
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#define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080)
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#define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00)
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#define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
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/*
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* TXRX_CSR5: OFDM TX BBP ID1.
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*/
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#define TXRX_CSR8 0x0450
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#define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
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#define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080)
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#define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00)
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#define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000)
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/*
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* TXRX_CSR9: TX ACK time-out.
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*/
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#define TXRX_CSR9 0x0452
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/*
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* TXRX_CSR10: Auto responder control.
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*/
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#define TXRX_CSR10 0x0454
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#define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
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/*
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* TXRX_CSR11: Auto responder basic rate.
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*/
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#define TXRX_CSR11 0x0456
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/*
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* ACK/CTS time registers.
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*/
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#define TXRX_CSR12 0x0458
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#define TXRX_CSR13 0x045a
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#define TXRX_CSR14 0x045c
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#define TXRX_CSR15 0x045e
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#define TXRX_CSR16 0x0460
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#define TXRX_CSR17 0x0462
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/*
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* TXRX_CSR18: Synchronization control register.
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*/
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#define TXRX_CSR18 0x0464
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#define TXRX_CSR18_OFFSET FIELD16(0x000f)
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#define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
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/*
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* TXRX_CSR19: Synchronization control register.
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* TSF_COUNT: Enable TSF auto counting.
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* TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
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* TBCN: Enable Tbcn with reload value.
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* BEACON_GEN: Enable beacon generator.
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*/
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#define TXRX_CSR19 0x0466
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#define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
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#define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
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#define TXRX_CSR19_TBCN FIELD16(0x0008)
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#define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
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/*
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* TXRX_CSR20: Tx BEACON offset time control register.
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* OFFSET: In units of usec.
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* BCN_EXPECT_WINDOW: Default: 2^CWmin
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*/
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#define TXRX_CSR20 0x0468
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#define TXRX_CSR20_OFFSET FIELD16(0x1fff)
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#define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
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/*
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* TXRX_CSR21
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*/
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#define TXRX_CSR21 0x046a
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/*
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* Encryption related CSRs.
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*
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*/
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/*
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* SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
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*/
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#define SEC_CSR0 0x0480
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#define SEC_CSR1 0x0482
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#define SEC_CSR2 0x0484
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#define SEC_CSR3 0x0486
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#define SEC_CSR4 0x0488
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#define SEC_CSR5 0x048a
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#define SEC_CSR6 0x048c
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#define SEC_CSR7 0x048e
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/*
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* SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
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*/
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#define SEC_CSR8 0x0490
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#define SEC_CSR9 0x0492
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#define SEC_CSR10 0x0494
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#define SEC_CSR11 0x0496
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#define SEC_CSR12 0x0498
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#define SEC_CSR13 0x049a
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#define SEC_CSR14 0x049c
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#define SEC_CSR15 0x049e
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/*
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* SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
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*/
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#define SEC_CSR16 0x04a0
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#define SEC_CSR17 0x04a2
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#define SEC_CSR18 0X04A4
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#define SEC_CSR19 0x04a6
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#define SEC_CSR20 0x04a8
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#define SEC_CSR21 0x04aa
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#define SEC_CSR22 0x04ac
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#define SEC_CSR23 0x04ae
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/*
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* SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
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*/
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#define SEC_CSR24 0x04b0
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#define SEC_CSR25 0x04b2
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#define SEC_CSR26 0x04b4
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#define SEC_CSR27 0x04b6
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#define SEC_CSR28 0x04b8
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#define SEC_CSR29 0x04ba
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#define SEC_CSR30 0x04bc
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#define SEC_CSR31 0x04be
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/*
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* PHY control registers.
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*/
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/*
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* PHY_CSR0: RF switching timing control.
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*/
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#define PHY_CSR0 0x04c0
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/*
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* PHY_CSR1: TX PA configuration.
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*/
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#define PHY_CSR1 0x04c2
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/*
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* MAC configuration registers.
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*/
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/*
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* PHY_CSR2: TX MAC configuration.
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* NOTE: Both register fields are complete dummy,
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* documentation and legacy drivers are unclear un
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* what this register means or what fields exists.
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*/
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#define PHY_CSR2 0x04c4
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#define PHY_CSR2_LNA FIELD16(0x0002)
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#define PHY_CSR2_LNA_MODE FIELD16(0x3000)
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/*
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* PHY_CSR3: RX MAC configuration.
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*/
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#define PHY_CSR3 0x04c6
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|
|
/*
|
|
* PHY_CSR4: Interface configuration.
|
|
*/
|
|
#define PHY_CSR4 0x04c8
|
|
#define PHY_CSR4_LOW_RF_LE FIELD16(0x0001)
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|
|
/*
|
|
* BBP pre-TX registers.
|
|
* PHY_CSR5: BBP pre-TX CCK.
|
|
*/
|
|
#define PHY_CSR5 0x04ca
|
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#define PHY_CSR5_CCK FIELD16(0x0003)
|
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#define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
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|
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/*
|
|
* BBP pre-TX registers.
|
|
* PHY_CSR6: BBP pre-TX OFDM.
|
|
*/
|
|
#define PHY_CSR6 0x04cc
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|
#define PHY_CSR6_OFDM FIELD16(0x0003)
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|
#define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
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|
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/*
|
|
* PHY_CSR7: BBP access register 0.
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|
* BBP_DATA: BBP data.
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* BBP_REG_ID: BBP register ID.
|
|
* BBP_READ_CONTROL: 0: write, 1: read.
|
|
*/
|
|
#define PHY_CSR7 0x04ce
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#define PHY_CSR7_DATA FIELD16(0x00ff)
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#define PHY_CSR7_REG_ID FIELD16(0x7f00)
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#define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
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|
|
/*
|
|
* PHY_CSR8: BBP access register 1.
|
|
* BBP_BUSY: ASIC is busy execute BBP programming.
|
|
*/
|
|
#define PHY_CSR8 0x04d0
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#define PHY_CSR8_BUSY FIELD16(0x0001)
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|
|
|
/*
|
|
* PHY_CSR9: RF access register.
|
|
* RF_VALUE: Register value + id to program into rf/if.
|
|
*/
|
|
#define PHY_CSR9 0x04d2
|
|
#define PHY_CSR9_RF_VALUE FIELD16(0xffff)
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|
|
|
/*
|
|
* PHY_CSR10: RF access register.
|
|
* RF_VALUE: Register value + id to program into rf/if.
|
|
* RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
|
|
* RF_IF_SELECT: Chip to program: 0: rf, 1: if.
|
|
* RF_PLL_LD: Rf pll_ld status.
|
|
* RF_BUSY: 1: asic is busy execute rf programming.
|
|
*/
|
|
#define PHY_CSR10 0x04d4
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#define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
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#define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
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#define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
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#define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
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#define PHY_CSR10_RF_BUSY FIELD16(0x8000)
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|
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/*
|
|
* STA_CSR0: FCS error count.
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|
* FCS_ERROR: FCS error count, cleared when read.
|
|
*/
|
|
#define STA_CSR0 0x04e0
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#define STA_CSR0_FCS_ERROR FIELD16(0xffff)
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|
|
/*
|
|
* STA_CSR1: PLCP error count.
|
|
*/
|
|
#define STA_CSR1 0x04e2
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|
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/*
|
|
* STA_CSR2: LONG error count.
|
|
*/
|
|
#define STA_CSR2 0x04e4
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|
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/*
|
|
* STA_CSR3: CCA false alarm.
|
|
* FALSE_CCA_ERROR: False CCA error count, cleared when read.
|
|
*/
|
|
#define STA_CSR3 0x04e6
|
|
#define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff)
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|
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/*
|
|
* STA_CSR4: RX FIFO overflow.
|
|
*/
|
|
#define STA_CSR4 0x04e8
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|
|
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/*
|
|
* STA_CSR5: Beacon sent counter.
|
|
*/
|
|
#define STA_CSR5 0x04ea
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|
|
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/*
|
|
* Statistics registers
|
|
*/
|
|
#define STA_CSR6 0x04ec
|
|
#define STA_CSR7 0x04ee
|
|
#define STA_CSR8 0x04f0
|
|
#define STA_CSR9 0x04f2
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|
#define STA_CSR10 0x04f4
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|
|
/*
|
|
* BBP registers.
|
|
* The wordsize of the BBP is 8 bits.
|
|
*/
|
|
|
|
/*
|
|
* R2: TX antenna control
|
|
*/
|
|
#define BBP_R2_TX_ANTENNA FIELD8(0x03)
|
|
#define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
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|
|
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/*
|
|
* R14: RX antenna control
|
|
*/
|
|
#define BBP_R14_RX_ANTENNA FIELD8(0x03)
|
|
#define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
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|
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/*
|
|
* RF registers.
|
|
*/
|
|
|
|
/*
|
|
* RF 1
|
|
*/
|
|
#define RF1_TUNER FIELD32(0x00020000)
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|
|
|
/*
|
|
* RF 3
|
|
*/
|
|
#define RF3_TUNER FIELD32(0x00000100)
|
|
#define RF3_TXPOWER FIELD32(0x00003e00)
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|
|
|
/*
|
|
* EEPROM contents.
|
|
*/
|
|
|
|
/*
|
|
* HW MAC address.
|
|
*/
|
|
#define EEPROM_MAC_ADDR_0 0x0002
|
|
#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
|
|
#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
|
|
#define EEPROM_MAC_ADDR1 0x0003
|
|
#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
|
|
#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
|
|
#define EEPROM_MAC_ADDR_2 0x0004
|
|
#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
|
|
#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
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|
|
|
/*
|
|
* EEPROM antenna.
|
|
* ANTENNA_NUM: Number of antenna's.
|
|
* TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
|
|
* RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
|
|
* LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
|
|
* DYN_TXAGC: Dynamic TX AGC control.
|
|
* HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
|
|
* RF_TYPE: Rf_type of this adapter.
|
|
*/
|
|
#define EEPROM_ANTENNA 0x000b
|
|
#define EEPROM_ANTENNA_NUM FIELD16(0x0003)
|
|
#define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
|
|
#define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
|
|
#define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
|
|
#define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
|
|
#define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
|
|
#define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
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|
|
|
/*
|
|
* EEPROM NIC config.
|
|
* CARDBUS_ACCEL: 0: enable, 1: disable.
|
|
* DYN_BBP_TUNE: 0: enable, 1: disable.
|
|
* CCK_TX_POWER: CCK TX power compensation.
|
|
*/
|
|
#define EEPROM_NIC 0x000c
|
|
#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
|
|
#define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
|
|
#define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
|
|
|
|
/*
|
|
* EEPROM geography.
|
|
* GEO: Default geography setting for device.
|
|
*/
|
|
#define EEPROM_GEOGRAPHY 0x000d
|
|
#define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
|
|
|
|
/*
|
|
* EEPROM BBP.
|
|
*/
|
|
#define EEPROM_BBP_START 0x000e
|
|
#define EEPROM_BBP_SIZE 16
|
|
#define EEPROM_BBP_VALUE FIELD16(0x00ff)
|
|
#define EEPROM_BBP_REG_ID FIELD16(0xff00)
|
|
|
|
/*
|
|
* EEPROM TXPOWER
|
|
*/
|
|
#define EEPROM_TXPOWER_START 0x001e
|
|
#define EEPROM_TXPOWER_SIZE 7
|
|
#define EEPROM_TXPOWER_1 FIELD16(0x00ff)
|
|
#define EEPROM_TXPOWER_2 FIELD16(0xff00)
|
|
|
|
/*
|
|
* EEPROM Tuning threshold
|
|
*/
|
|
#define EEPROM_BBPTUNE 0x0030
|
|
#define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
|
|
|
|
/*
|
|
* EEPROM BBP R24 Tuning.
|
|
*/
|
|
#define EEPROM_BBPTUNE_R24 0x0031
|
|
#define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
|
|
#define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
|
|
|
|
/*
|
|
* EEPROM BBP R25 Tuning.
|
|
*/
|
|
#define EEPROM_BBPTUNE_R25 0x0032
|
|
#define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
|
|
#define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
|
|
|
|
/*
|
|
* EEPROM BBP R24 Tuning.
|
|
*/
|
|
#define EEPROM_BBPTUNE_R61 0x0033
|
|
#define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
|
|
#define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
|
|
|
|
/*
|
|
* EEPROM BBP VGC Tuning.
|
|
*/
|
|
#define EEPROM_BBPTUNE_VGC 0x0034
|
|
#define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
|
|
#define EEPROM_BBPTUNE_VGCLOWER FIELD16(0xff00)
|
|
|
|
/*
|
|
* EEPROM BBP R17 Tuning.
|
|
*/
|
|
#define EEPROM_BBPTUNE_R17 0x0035
|
|
#define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
|
|
#define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
|
|
|
|
/*
|
|
* RSSI <-> dBm offset calibration
|
|
*/
|
|
#define EEPROM_CALIBRATE_OFFSET 0x0036
|
|
#define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
|
|
|
|
/*
|
|
* DMA descriptor defines.
|
|
*/
|
|
#define TXD_DESC_SIZE ( 5 * sizeof(__le32) )
|
|
#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
|
|
|
|
/*
|
|
* TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
|
|
*/
|
|
|
|
/*
|
|
* Word0
|
|
*/
|
|
#define TXD_W0_PACKET_ID FIELD32(0x0000000f)
|
|
#define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
|
|
#define TXD_W0_MORE_FRAG FIELD32(0x00000100)
|
|
#define TXD_W0_ACK FIELD32(0x00000200)
|
|
#define TXD_W0_TIMESTAMP FIELD32(0x00000400)
|
|
#define TXD_W0_OFDM FIELD32(0x00000800)
|
|
#define TXD_W0_NEW_SEQ FIELD32(0x00001000)
|
|
#define TXD_W0_IFS FIELD32(0x00006000)
|
|
#define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
|
|
#define TXD_W0_CIPHER FIELD32(0x20000000)
|
|
#define TXD_W0_KEY_ID FIELD32(0xc0000000)
|
|
|
|
/*
|
|
* Word1
|
|
*/
|
|
#define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
|
|
#define TXD_W1_AIFS FIELD32(0x000000c0)
|
|
#define TXD_W1_CWMIN FIELD32(0x00000f00)
|
|
#define TXD_W1_CWMAX FIELD32(0x0000f000)
|
|
|
|
/*
|
|
* Word2: PLCP information
|
|
*/
|
|
#define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
|
|
#define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
|
|
#define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
|
|
#define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
|
|
|
|
/*
|
|
* Word3
|
|
*/
|
|
#define TXD_W3_IV FIELD32(0xffffffff)
|
|
|
|
/*
|
|
* Word4
|
|
*/
|
|
#define TXD_W4_EIV FIELD32(0xffffffff)
|
|
|
|
/*
|
|
* RX descriptor format for RX Ring.
|
|
*/
|
|
|
|
/*
|
|
* Word0
|
|
*/
|
|
#define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
|
|
#define RXD_W0_MULTICAST FIELD32(0x00000004)
|
|
#define RXD_W0_BROADCAST FIELD32(0x00000008)
|
|
#define RXD_W0_MY_BSS FIELD32(0x00000010)
|
|
#define RXD_W0_CRC_ERROR FIELD32(0x00000020)
|
|
#define RXD_W0_OFDM FIELD32(0x00000040)
|
|
#define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
|
|
#define RXD_W0_CIPHER FIELD32(0x00000100)
|
|
#define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
|
|
#define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
|
|
|
|
/*
|
|
* Word1
|
|
*/
|
|
#define RXD_W1_RSSI FIELD32(0x000000ff)
|
|
#define RXD_W1_SIGNAL FIELD32(0x0000ff00)
|
|
|
|
/*
|
|
* Word2
|
|
*/
|
|
#define RXD_W2_IV FIELD32(0xffffffff)
|
|
|
|
/*
|
|
* Word3
|
|
*/
|
|
#define RXD_W3_EIV FIELD32(0xffffffff)
|
|
|
|
/*
|
|
* Macro's for converting txpower from EEPROM to dscape value
|
|
* and from dscape value to register value.
|
|
*/
|
|
#define MIN_TXPOWER 0
|
|
#define MAX_TXPOWER 31
|
|
#define DEFAULT_TXPOWER 24
|
|
|
|
#define TXPOWER_FROM_DEV(__txpower) \
|
|
({ \
|
|
((__txpower) > MAX_TXPOWER) ? \
|
|
DEFAULT_TXPOWER : (__txpower); \
|
|
})
|
|
|
|
#define TXPOWER_TO_DEV(__txpower) \
|
|
({ \
|
|
((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
|
|
(((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
|
|
(__txpower)); \
|
|
})
|
|
|
|
#endif /* RT2500USB_H */
|