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3b155e873a
DT documentation for SPI controller added. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Mark Brown <broonie@kernel.org>
38 lines
1.5 KiB
Plaintext
38 lines
1.5 KiB
Plaintext
SiFive SPI controller Device Tree Bindings
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Required properties:
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- compatible : Should be "sifive,<chip>-spi" and "sifive,spi<version>".
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Supported compatible strings are:
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"sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
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onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
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SPI v0 IP block with no chip integration tweaks.
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Please refer to sifive-blocks-ip-versioning.txt for details
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- reg : Physical base address and size of SPI registers map
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A second (optional) range can indicate memory mapped flash
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- interrupts : Must contain one entry
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- interrupt-parent : Must be core interrupt controller
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- clocks : Must reference the frequency given to the controller
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- #address-cells : Must be '1', indicating which CS to use
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- #size-cells : Must be '0'
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Optional properties:
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- sifive,fifo-depth : Depth of hardware queues; defaults to 8
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- sifive,max-bits-per-word : Maximum bits per word; defaults to 8
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SPI RTL that corresponds to the IP block version numbers can be found here:
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https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
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Example:
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spi: spi@10040000 {
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compatible = "sifive,fu540-c000-spi", "sifive,spi0";
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reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
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interrupt-parent = <&plic>;
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interrupts = <51>;
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clocks = <&tlclk>;
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#address-cells = <1>;
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#size-cells = <0>;
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sifive,fifo-depth = <8>;
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sifive,max-bits-per-word = <8>;
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};
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