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percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: Tejun Heo <tj@kernel.org> Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
472 lines
13 KiB
C
472 lines
13 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2000-2007 Silicon Graphics, Inc. All Rights Reserved.
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*/
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#include <linux/module.h>
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#include <asm/sn/nodepda.h>
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#include <asm/sn/addrs.h>
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#include <asm/sn/arch.h>
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#include <asm/sn/sn_cpuid.h>
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#include <asm/sn/pda.h>
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#include <asm/sn/shubio.h>
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#include <asm/nodedata.h>
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#include <asm/delay.h>
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#include <linux/bootmem.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <asm/sn/bte.h>
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#ifndef L1_CACHE_MASK
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#define L1_CACHE_MASK (L1_CACHE_BYTES - 1)
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#endif
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/* two interfaces on two btes */
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#define MAX_INTERFACES_TO_TRY 4
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#define MAX_NODES_TO_TRY 2
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static struct bteinfo_s *bte_if_on_node(nasid_t nasid, int interface)
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{
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nodepda_t *tmp_nodepda;
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if (nasid_to_cnodeid(nasid) == -1)
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return (struct bteinfo_s *)NULL;
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tmp_nodepda = NODEPDA(nasid_to_cnodeid(nasid));
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return &tmp_nodepda->bte_if[interface];
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}
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static inline void bte_start_transfer(struct bteinfo_s *bte, u64 len, u64 mode)
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{
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if (is_shub2()) {
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BTE_CTRL_STORE(bte, (IBLS_BUSY | ((len) | (mode) << 24)));
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} else {
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BTE_LNSTAT_STORE(bte, len);
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BTE_CTRL_STORE(bte, mode);
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}
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}
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/************************************************************************
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* Block Transfer Engine copy related functions.
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*
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***********************************************************************/
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/*
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* bte_copy(src, dest, len, mode, notification)
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*
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* Use the block transfer engine to move kernel memory from src to dest
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* using the assigned mode.
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*
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* Parameters:
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* src - physical address of the transfer source.
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* dest - physical address of the transfer destination.
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* len - number of bytes to transfer from source to dest.
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* mode - hardware defined. See reference information
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* for IBCT0/1 in the SHUB Programmers Reference
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* notification - kernel virtual address of the notification cache
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* line. If NULL, the default is used and
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* the bte_copy is synchronous.
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*
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* NOTE: This function requires src, dest, and len to
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* be cacheline aligned.
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*/
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bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
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{
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u64 transfer_size;
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u64 transfer_stat;
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u64 notif_phys_addr;
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struct bteinfo_s *bte;
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bte_result_t bte_status;
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unsigned long irq_flags;
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unsigned long itc_end = 0;
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int nasid_to_try[MAX_NODES_TO_TRY];
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int my_nasid = cpuid_to_nasid(raw_smp_processor_id());
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int bte_if_index, nasid_index;
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int bte_first, btes_per_node = BTES_PER_NODE;
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BTE_PRINTK(("bte_copy(0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%p)\n",
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src, dest, len, mode, notification));
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if (len == 0) {
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return BTE_SUCCESS;
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}
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BUG_ON(len & L1_CACHE_MASK);
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BUG_ON(src & L1_CACHE_MASK);
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BUG_ON(dest & L1_CACHE_MASK);
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BUG_ON(len > BTE_MAX_XFER);
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/*
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* Start with interface corresponding to cpu number
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*/
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bte_first = raw_smp_processor_id() % btes_per_node;
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if (mode & BTE_USE_DEST) {
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/* try remote then local */
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nasid_to_try[0] = NASID_GET(dest);
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if (mode & BTE_USE_ANY) {
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nasid_to_try[1] = my_nasid;
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} else {
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nasid_to_try[1] = (int)NULL;
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}
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} else {
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/* try local then remote */
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nasid_to_try[0] = my_nasid;
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if (mode & BTE_USE_ANY) {
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nasid_to_try[1] = NASID_GET(dest);
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} else {
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nasid_to_try[1] = (int)NULL;
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}
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}
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retry_bteop:
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do {
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local_irq_save(irq_flags);
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bte_if_index = bte_first;
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nasid_index = 0;
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/* Attempt to lock one of the BTE interfaces. */
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while (nasid_index < MAX_NODES_TO_TRY) {
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bte = bte_if_on_node(nasid_to_try[nasid_index],bte_if_index);
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if (bte == NULL) {
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nasid_index++;
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continue;
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}
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if (spin_trylock(&bte->spinlock)) {
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if (!(*bte->most_rcnt_na & BTE_WORD_AVAILABLE) ||
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(BTE_LNSTAT_LOAD(bte) & BTE_ACTIVE)) {
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/* Got the lock but BTE still busy */
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spin_unlock(&bte->spinlock);
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} else {
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/* we got the lock and it's not busy */
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break;
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}
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}
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bte_if_index = (bte_if_index + 1) % btes_per_node; /* Next interface */
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if (bte_if_index == bte_first) {
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/*
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* We've tried all interfaces on this node
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*/
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nasid_index++;
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}
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bte = NULL;
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}
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if (bte != NULL) {
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break;
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}
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local_irq_restore(irq_flags);
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if (!(mode & BTE_WACQUIRE)) {
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return BTEFAIL_NOTAVAIL;
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}
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} while (1);
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if (notification == NULL) {
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/* User does not want to be notified. */
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bte->most_rcnt_na = &bte->notify;
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} else {
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bte->most_rcnt_na = notification;
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}
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/* Calculate the number of cache lines to transfer. */
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transfer_size = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK);
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/* Initialize the notification to a known value. */
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*bte->most_rcnt_na = BTE_WORD_BUSY;
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notif_phys_addr = (u64)bte->most_rcnt_na;
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/* Set the source and destination registers */
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BTE_PRINTKV(("IBSA = 0x%lx)\n", src));
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BTE_SRC_STORE(bte, src);
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BTE_PRINTKV(("IBDA = 0x%lx)\n", dest));
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BTE_DEST_STORE(bte, dest);
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/* Set the notification register */
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BTE_PRINTKV(("IBNA = 0x%lx)\n", notif_phys_addr));
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BTE_NOTIF_STORE(bte, notif_phys_addr);
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/* Initiate the transfer */
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BTE_PRINTK(("IBCT = 0x%lx)\n", BTE_VALID_MODE(mode)));
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bte_start_transfer(bte, transfer_size, BTE_VALID_MODE(mode));
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itc_end = ia64_get_itc() + (40000000 * local_cpu_data->cyc_per_usec);
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spin_unlock_irqrestore(&bte->spinlock, irq_flags);
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if (notification != NULL) {
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return BTE_SUCCESS;
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}
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while ((transfer_stat = *bte->most_rcnt_na) == BTE_WORD_BUSY) {
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cpu_relax();
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if (ia64_get_itc() > itc_end) {
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BTE_PRINTK(("BTE timeout nasid 0x%x bte%d IBLS = 0x%lx na 0x%lx\n",
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NASID_GET(bte->bte_base_addr), bte->bte_num,
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BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na) );
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bte->bte_error_count++;
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bte->bh_error = IBLS_ERROR;
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bte_error_handler((unsigned long)NODEPDA(bte->bte_cnode));
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*bte->most_rcnt_na = BTE_WORD_AVAILABLE;
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goto retry_bteop;
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}
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}
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BTE_PRINTKV((" Delay Done. IBLS = 0x%lx, most_rcnt_na = 0x%lx\n",
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BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
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if (transfer_stat & IBLS_ERROR) {
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bte_status = BTE_GET_ERROR_STATUS(transfer_stat);
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} else {
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bte_status = BTE_SUCCESS;
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}
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*bte->most_rcnt_na = BTE_WORD_AVAILABLE;
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BTE_PRINTK(("Returning status is 0x%lx and most_rcnt_na is 0x%lx\n",
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BTE_LNSTAT_LOAD(bte), *bte->most_rcnt_na));
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return bte_status;
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}
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EXPORT_SYMBOL(bte_copy);
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/*
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* bte_unaligned_copy(src, dest, len, mode)
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*
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* use the block transfer engine to move kernel
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* memory from src to dest using the assigned mode.
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*
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* Parameters:
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* src - physical address of the transfer source.
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* dest - physical address of the transfer destination.
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* len - number of bytes to transfer from source to dest.
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* mode - hardware defined. See reference information
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* for IBCT0/1 in the SGI documentation.
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*
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* NOTE: If the source, dest, and len are all cache line aligned,
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* then it would be _FAR_ preferable to use bte_copy instead.
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*/
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bte_result_t bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode)
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{
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int destFirstCacheOffset;
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u64 headBteSource;
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u64 headBteLen;
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u64 headBcopySrcOffset;
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u64 headBcopyDest;
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u64 headBcopyLen;
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u64 footBteSource;
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u64 footBteLen;
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u64 footBcopyDest;
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u64 footBcopyLen;
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bte_result_t rv;
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char *bteBlock, *bteBlock_unaligned;
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if (len == 0) {
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return BTE_SUCCESS;
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}
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/* temporary buffer used during unaligned transfers */
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bteBlock_unaligned = kmalloc(len + 3 * L1_CACHE_BYTES, GFP_KERNEL);
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if (bteBlock_unaligned == NULL) {
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return BTEFAIL_NOTAVAIL;
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}
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bteBlock = (char *)L1_CACHE_ALIGN((u64) bteBlock_unaligned);
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headBcopySrcOffset = src & L1_CACHE_MASK;
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destFirstCacheOffset = dest & L1_CACHE_MASK;
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/*
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* At this point, the transfer is broken into
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* (up to) three sections. The first section is
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* from the start address to the first physical
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* cache line, the second is from the first physical
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* cache line to the last complete cache line,
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* and the third is from the last cache line to the
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* end of the buffer. The first and third sections
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* are handled by bte copying into a temporary buffer
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* and then bcopy'ing the necessary section into the
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* final location. The middle section is handled with
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* a standard bte copy.
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*
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* One nasty exception to the above rule is when the
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* source and destination are not symmetrically
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* mis-aligned. If the source offset from the first
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* cache line is different from the destination offset,
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* we make the first section be the entire transfer
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* and the bcopy the entire block into place.
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*/
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if (headBcopySrcOffset == destFirstCacheOffset) {
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/*
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* Both the source and destination are the same
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* distance from a cache line boundary so we can
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* use the bte to transfer the bulk of the
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* data.
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*/
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headBteSource = src & ~L1_CACHE_MASK;
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headBcopyDest = dest;
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if (headBcopySrcOffset) {
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headBcopyLen =
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(len >
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(L1_CACHE_BYTES -
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headBcopySrcOffset) ? L1_CACHE_BYTES
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- headBcopySrcOffset : len);
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headBteLen = L1_CACHE_BYTES;
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} else {
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headBcopyLen = 0;
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headBteLen = 0;
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}
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if (len > headBcopyLen) {
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footBcopyLen = (len - headBcopyLen) & L1_CACHE_MASK;
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footBteLen = L1_CACHE_BYTES;
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footBteSource = src + len - footBcopyLen;
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footBcopyDest = dest + len - footBcopyLen;
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if (footBcopyDest == (headBcopyDest + headBcopyLen)) {
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/*
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* We have two contiguous bcopy
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* blocks. Merge them.
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*/
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headBcopyLen += footBcopyLen;
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headBteLen += footBteLen;
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} else if (footBcopyLen > 0) {
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rv = bte_copy(footBteSource,
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ia64_tpa((unsigned long)bteBlock),
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footBteLen, mode, NULL);
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if (rv != BTE_SUCCESS) {
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kfree(bteBlock_unaligned);
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return rv;
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}
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memcpy(__va(footBcopyDest),
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(char *)bteBlock, footBcopyLen);
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}
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} else {
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footBcopyLen = 0;
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footBteLen = 0;
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}
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if (len > (headBcopyLen + footBcopyLen)) {
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/* now transfer the middle. */
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rv = bte_copy((src + headBcopyLen),
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(dest +
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headBcopyLen),
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(len - headBcopyLen -
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footBcopyLen), mode, NULL);
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if (rv != BTE_SUCCESS) {
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kfree(bteBlock_unaligned);
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return rv;
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}
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}
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} else {
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/*
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* The transfer is not symmetric, we will
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* allocate a buffer large enough for all the
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* data, bte_copy into that buffer and then
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* bcopy to the destination.
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*/
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headBcopySrcOffset = src & L1_CACHE_MASK;
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headBcopyDest = dest;
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headBcopyLen = len;
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headBteSource = src - headBcopySrcOffset;
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/* Add the leading and trailing bytes from source */
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headBteLen = L1_CACHE_ALIGN(len + headBcopySrcOffset);
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}
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if (headBcopyLen > 0) {
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rv = bte_copy(headBteSource,
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ia64_tpa((unsigned long)bteBlock), headBteLen,
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mode, NULL);
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if (rv != BTE_SUCCESS) {
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kfree(bteBlock_unaligned);
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return rv;
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}
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memcpy(__va(headBcopyDest), ((char *)bteBlock +
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headBcopySrcOffset), headBcopyLen);
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}
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kfree(bteBlock_unaligned);
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return BTE_SUCCESS;
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}
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EXPORT_SYMBOL(bte_unaligned_copy);
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/************************************************************************
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* Block Transfer Engine initialization functions.
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*
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***********************************************************************/
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/*
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* bte_init_node(nodepda, cnode)
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*
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* Initialize the nodepda structure with BTE base addresses and
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* spinlocks.
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*/
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void bte_init_node(nodepda_t * mynodepda, cnodeid_t cnode)
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{
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int i;
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/*
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* Indicate that all the block transfer engines on this node
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* are available.
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*/
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/*
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* Allocate one bte_recover_t structure per node. It holds
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* the recovery lock for node. All the bte interface structures
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* will point at this one bte_recover structure to get the lock.
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*/
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spin_lock_init(&mynodepda->bte_recovery_lock);
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init_timer(&mynodepda->bte_recovery_timer);
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mynodepda->bte_recovery_timer.function = bte_error_handler;
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mynodepda->bte_recovery_timer.data = (unsigned long)mynodepda;
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for (i = 0; i < BTES_PER_NODE; i++) {
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u64 *base_addr;
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/* Which link status register should we use? */
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base_addr = (u64 *)
|
|
REMOTE_HUB_ADDR(cnodeid_to_nasid(cnode), BTE_BASE_ADDR(i));
|
|
mynodepda->bte_if[i].bte_base_addr = base_addr;
|
|
mynodepda->bte_if[i].bte_source_addr = BTE_SOURCE_ADDR(base_addr);
|
|
mynodepda->bte_if[i].bte_destination_addr = BTE_DEST_ADDR(base_addr);
|
|
mynodepda->bte_if[i].bte_control_addr = BTE_CTRL_ADDR(base_addr);
|
|
mynodepda->bte_if[i].bte_notify_addr = BTE_NOTIF_ADDR(base_addr);
|
|
|
|
/*
|
|
* Initialize the notification and spinlock
|
|
* so the first transfer can occur.
|
|
*/
|
|
mynodepda->bte_if[i].most_rcnt_na =
|
|
&(mynodepda->bte_if[i].notify);
|
|
mynodepda->bte_if[i].notify = BTE_WORD_AVAILABLE;
|
|
spin_lock_init(&mynodepda->bte_if[i].spinlock);
|
|
|
|
mynodepda->bte_if[i].bte_cnode = cnode;
|
|
mynodepda->bte_if[i].bte_error_count = 0;
|
|
mynodepda->bte_if[i].bte_num = i;
|
|
mynodepda->bte_if[i].cleanup_active = 0;
|
|
mynodepda->bte_if[i].bh_error = 0;
|
|
}
|
|
|
|
}
|