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13150149aa
Kernel mode NEON can be used in task or softirq context, but only in a non-nesting manner, i.e., softirq context is only permitted if the interrupt was not taken at a point where the kernel was using the NEON in task context. This means all users of kernel mode NEON have to be aware of this limitation, and either need to provide scalar fallbacks that may be much slower (up to 20x for AES instructions) and potentially less safe, or use an asynchronous interface that defers processing to a later time when the NEON is guaranteed to be available. Given that grabbing and releasing the NEON is cheap, we can relax this restriction, by increasing the granularity of kernel mode NEON code, and always disabling softirq processing while the NEON is being used in task context. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Acked-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210302090118.30666-4-ardb@kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
207 lines
6.5 KiB
ArmAsm
207 lines
6.5 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
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*
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* Copyright (C) 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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.irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
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.set .Lq\b, \b
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.set .Lv\b\().2d, \b
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.endr
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.macro sha512h, rd, rn, rm
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.inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
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.endm
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.macro sha512h2, rd, rn, rm
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.inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
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.endm
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.macro sha512su0, rd, rn
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.inst 0xcec08000 | .L\rd | (.L\rn << 5)
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.endm
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.macro sha512su1, rd, rn, rm
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.inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
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.endm
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/*
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* The SHA-512 round constants
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*/
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.section ".rodata", "a"
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.align 4
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.Lsha512_rcon:
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.quad 0x428a2f98d728ae22, 0x7137449123ef65cd
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.quad 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
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.quad 0x3956c25bf348b538, 0x59f111f1b605d019
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.quad 0x923f82a4af194f9b, 0xab1c5ed5da6d8118
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.quad 0xd807aa98a3030242, 0x12835b0145706fbe
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.quad 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
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.quad 0x72be5d74f27b896f, 0x80deb1fe3b1696b1
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.quad 0x9bdc06a725c71235, 0xc19bf174cf692694
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.quad 0xe49b69c19ef14ad2, 0xefbe4786384f25e3
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.quad 0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65
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.quad 0x2de92c6f592b0275, 0x4a7484aa6ea6e483
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.quad 0x5cb0a9dcbd41fbd4, 0x76f988da831153b5
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.quad 0x983e5152ee66dfab, 0xa831c66d2db43210
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.quad 0xb00327c898fb213f, 0xbf597fc7beef0ee4
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.quad 0xc6e00bf33da88fc2, 0xd5a79147930aa725
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.quad 0x06ca6351e003826f, 0x142929670a0e6e70
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.quad 0x27b70a8546d22ffc, 0x2e1b21385c26c926
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.quad 0x4d2c6dfc5ac42aed, 0x53380d139d95b3df
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.quad 0x650a73548baf63de, 0x766a0abb3c77b2a8
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.quad 0x81c2c92e47edaee6, 0x92722c851482353b
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.quad 0xa2bfe8a14cf10364, 0xa81a664bbc423001
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.quad 0xc24b8b70d0f89791, 0xc76c51a30654be30
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.quad 0xd192e819d6ef5218, 0xd69906245565a910
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.quad 0xf40e35855771202a, 0x106aa07032bbd1b8
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.quad 0x19a4c116b8d2d0c8, 0x1e376c085141ab53
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.quad 0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8
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.quad 0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb
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.quad 0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3
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.quad 0x748f82ee5defb2fc, 0x78a5636f43172f60
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.quad 0x84c87814a1f0ab72, 0x8cc702081a6439ec
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.quad 0x90befffa23631e28, 0xa4506cebde82bde9
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.quad 0xbef9a3f7b2c67915, 0xc67178f2e372532b
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.quad 0xca273eceea26619c, 0xd186b8c721c0c207
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.quad 0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178
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.quad 0x06f067aa72176fba, 0x0a637dc5a2c898a6
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.quad 0x113f9804bef90dae, 0x1b710b35131c471b
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.quad 0x28db77f523047d84, 0x32caab7b40c72493
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.quad 0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c
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.quad 0x4cc5d4becb3e42b6, 0x597f299cfc657e2a
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.quad 0x5fcb6fab3ad6faec, 0x6c44198c4a475817
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.macro dround, i0, i1, i2, i3, i4, rc0, rc1, in0, in1, in2, in3, in4
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.ifnb \rc1
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ld1 {v\rc1\().2d}, [x4], #16
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.endif
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add v5.2d, v\rc0\().2d, v\in0\().2d
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ext v6.16b, v\i2\().16b, v\i3\().16b, #8
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ext v5.16b, v5.16b, v5.16b, #8
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ext v7.16b, v\i1\().16b, v\i2\().16b, #8
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add v\i3\().2d, v\i3\().2d, v5.2d
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.ifnb \in1
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ext v5.16b, v\in3\().16b, v\in4\().16b, #8
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sha512su0 v\in0\().2d, v\in1\().2d
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.endif
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sha512h q\i3, q6, v7.2d
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.ifnb \in1
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sha512su1 v\in0\().2d, v\in2\().2d, v5.2d
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.endif
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add v\i4\().2d, v\i1\().2d, v\i3\().2d
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sha512h2 q\i3, q\i1, v\i0\().2d
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.endm
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/*
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* void sha512_ce_transform(struct sha512_state *sst, u8 const *src,
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* int blocks)
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*/
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.text
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SYM_FUNC_START(sha512_ce_transform)
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/* load state */
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ld1 {v8.2d-v11.2d}, [x0]
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/* load first 4 round constants */
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adr_l x3, .Lsha512_rcon
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ld1 {v20.2d-v23.2d}, [x3], #64
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/* load input */
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0: ld1 {v12.2d-v15.2d}, [x1], #64
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ld1 {v16.2d-v19.2d}, [x1], #64
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sub w2, w2, #1
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CPU_LE( rev64 v12.16b, v12.16b )
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CPU_LE( rev64 v13.16b, v13.16b )
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CPU_LE( rev64 v14.16b, v14.16b )
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CPU_LE( rev64 v15.16b, v15.16b )
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CPU_LE( rev64 v16.16b, v16.16b )
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CPU_LE( rev64 v17.16b, v17.16b )
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CPU_LE( rev64 v18.16b, v18.16b )
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CPU_LE( rev64 v19.16b, v19.16b )
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mov x4, x3 // rc pointer
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mov v0.16b, v8.16b
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mov v1.16b, v9.16b
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mov v2.16b, v10.16b
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mov v3.16b, v11.16b
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// v0 ab cd -- ef gh ab
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// v1 cd -- ef gh ab cd
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// v2 ef gh ab cd -- ef
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// v3 gh ab cd -- ef gh
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// v4 -- ef gh ab cd --
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dround 0, 1, 2, 3, 4, 20, 24, 12, 13, 19, 16, 17
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dround 3, 0, 4, 2, 1, 21, 25, 13, 14, 12, 17, 18
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dround 2, 3, 1, 4, 0, 22, 26, 14, 15, 13, 18, 19
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dround 4, 2, 0, 1, 3, 23, 27, 15, 16, 14, 19, 12
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dround 1, 4, 3, 0, 2, 24, 28, 16, 17, 15, 12, 13
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dround 0, 1, 2, 3, 4, 25, 29, 17, 18, 16, 13, 14
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dround 3, 0, 4, 2, 1, 26, 30, 18, 19, 17, 14, 15
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dround 2, 3, 1, 4, 0, 27, 31, 19, 12, 18, 15, 16
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dround 4, 2, 0, 1, 3, 28, 24, 12, 13, 19, 16, 17
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dround 1, 4, 3, 0, 2, 29, 25, 13, 14, 12, 17, 18
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dround 0, 1, 2, 3, 4, 30, 26, 14, 15, 13, 18, 19
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dround 3, 0, 4, 2, 1, 31, 27, 15, 16, 14, 19, 12
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dround 2, 3, 1, 4, 0, 24, 28, 16, 17, 15, 12, 13
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dround 4, 2, 0, 1, 3, 25, 29, 17, 18, 16, 13, 14
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dround 1, 4, 3, 0, 2, 26, 30, 18, 19, 17, 14, 15
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dround 0, 1, 2, 3, 4, 27, 31, 19, 12, 18, 15, 16
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dround 3, 0, 4, 2, 1, 28, 24, 12, 13, 19, 16, 17
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dround 2, 3, 1, 4, 0, 29, 25, 13, 14, 12, 17, 18
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dround 4, 2, 0, 1, 3, 30, 26, 14, 15, 13, 18, 19
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dround 1, 4, 3, 0, 2, 31, 27, 15, 16, 14, 19, 12
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dround 0, 1, 2, 3, 4, 24, 28, 16, 17, 15, 12, 13
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dround 3, 0, 4, 2, 1, 25, 29, 17, 18, 16, 13, 14
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dround 2, 3, 1, 4, 0, 26, 30, 18, 19, 17, 14, 15
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dround 4, 2, 0, 1, 3, 27, 31, 19, 12, 18, 15, 16
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dround 1, 4, 3, 0, 2, 28, 24, 12, 13, 19, 16, 17
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dround 0, 1, 2, 3, 4, 29, 25, 13, 14, 12, 17, 18
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dround 3, 0, 4, 2, 1, 30, 26, 14, 15, 13, 18, 19
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dround 2, 3, 1, 4, 0, 31, 27, 15, 16, 14, 19, 12
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dround 4, 2, 0, 1, 3, 24, 28, 16, 17, 15, 12, 13
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dround 1, 4, 3, 0, 2, 25, 29, 17, 18, 16, 13, 14
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dround 0, 1, 2, 3, 4, 26, 30, 18, 19, 17, 14, 15
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dround 3, 0, 4, 2, 1, 27, 31, 19, 12, 18, 15, 16
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dround 2, 3, 1, 4, 0, 28, 24, 12
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dround 4, 2, 0, 1, 3, 29, 25, 13
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dround 1, 4, 3, 0, 2, 30, 26, 14
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dround 0, 1, 2, 3, 4, 31, 27, 15
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dround 3, 0, 4, 2, 1, 24, , 16
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dround 2, 3, 1, 4, 0, 25, , 17
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dround 4, 2, 0, 1, 3, 26, , 18
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dround 1, 4, 3, 0, 2, 27, , 19
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/* update state */
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add v8.2d, v8.2d, v0.2d
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add v9.2d, v9.2d, v1.2d
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add v10.2d, v10.2d, v2.2d
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add v11.2d, v11.2d, v3.2d
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cond_yield 3f, x4, x5
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/* handled all input blocks? */
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cbnz w2, 0b
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/* store new state */
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3: st1 {v8.2d-v11.2d}, [x0]
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mov w0, w2
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ret
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SYM_FUNC_END(sha512_ce_transform)
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