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2fcf533508
request_irq() is preferred over setup_irq(). Invocations of setup_irq() occur after memory allocators are ready. Per tglx[1], setup_irq() existed in olden days when allocators were not ready by the time early interrupts were initialized. Hence replace setup_irq() by request_irq(). [1] https://lkml.kernel.org/r/alpine.DEB.2.20.1710191609480.1971@nanos Link: https://lore.kernel.org/r/20200327124437.4239-1-afzal.mohd.ma@gmail.com Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com> Acked-by: Lubomir Rintel <lkundrak@v3.sk> Tested-by: Lubomir Rintel <lkundrak@v3.sk> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
225 lines
4.9 KiB
C
225 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* linux/arch/arm/mach-mmp/time.c
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*
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* Support for clocksource and clockevents
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*
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* Copyright (C) 2008 Marvell International Ltd.
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* All rights reserved.
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*
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* 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
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* 2008-10-08: Bin Yang <bin.yang@marvell.com>
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*
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* The timers module actually includes three timers, each timer with up to
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* three match comparators. Timer #0 is used here in free-running mode as
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* the clock source, and match comparator #1 used as clock event device.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <asm/mach/time.h>
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#include "addr-map.h"
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#include "regs-timers.h"
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#include "regs-apbc.h"
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#include "irqs.h"
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#include <linux/soc/mmp/cputype.h>
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#include "clock.h"
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#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
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#define MAX_DELTA (0xfffffffe)
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#define MIN_DELTA (16)
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static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
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/*
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* FIXME: the timer needs some delay to stablize the counter capture
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*/
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static inline uint32_t timer_read(void)
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{
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int delay = 100;
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__raw_writel(1, mmp_timer_base + TMR_CVWR(1));
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while (delay--)
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cpu_relax();
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return __raw_readl(mmp_timer_base + TMR_CVWR(1));
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}
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static u64 notrace mmp_read_sched_clock(void)
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{
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return timer_read();
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *c = dev_id;
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/*
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* Clear pending interrupt status.
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*/
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__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
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/*
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* Disable timer 0.
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*/
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__raw_writel(0x02, mmp_timer_base + TMR_CER);
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c->event_handler(c);
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return IRQ_HANDLED;
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}
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static int timer_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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unsigned long flags;
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local_irq_save(flags);
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/*
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* Disable timer 0.
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*/
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__raw_writel(0x02, mmp_timer_base + TMR_CER);
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/*
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* Clear and enable timer match 0 interrupt.
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*/
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__raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
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__raw_writel(0x01, mmp_timer_base + TMR_IER(0));
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/*
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* Setup new clockevent timer value.
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*/
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__raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
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/*
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* Enable timer 0.
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*/
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__raw_writel(0x03, mmp_timer_base + TMR_CER);
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local_irq_restore(flags);
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return 0;
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}
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static int timer_set_shutdown(struct clock_event_device *evt)
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{
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unsigned long flags;
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local_irq_save(flags);
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/* disable the matching interrupt */
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__raw_writel(0x00, mmp_timer_base + TMR_IER(0));
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local_irq_restore(flags);
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return 0;
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}
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static struct clock_event_device ckevt = {
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.name = "clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.set_next_event = timer_set_next_event,
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.set_state_shutdown = timer_set_shutdown,
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.set_state_oneshot = timer_set_shutdown,
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};
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static u64 clksrc_read(struct clocksource *cs)
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{
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return timer_read();
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}
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static struct clocksource cksrc = {
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.name = "clocksource",
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.rating = 200,
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.read = clksrc_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init timer_config(void)
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{
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uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
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__raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
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ccr &= (cpu_is_mmp2() || cpu_is_mmp3()) ?
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(TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
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(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
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__raw_writel(ccr, mmp_timer_base + TMR_CCR);
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/* set timer 0 to periodic mode, and timer 1 to free-running mode */
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__raw_writel(0x2, mmp_timer_base + TMR_CMR);
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__raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
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__raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
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__raw_writel(0x0, mmp_timer_base + TMR_IER(0));
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__raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
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__raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
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__raw_writel(0x0, mmp_timer_base + TMR_IER(1));
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/* enable timer 1 counter */
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__raw_writel(0x2, mmp_timer_base + TMR_CER);
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}
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void __init mmp_timer_init(int irq, unsigned long rate)
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{
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timer_config();
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sched_clock_register(mmp_read_sched_clock, 32, rate);
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ckevt.cpumask = cpumask_of(0);
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if (request_irq(irq, timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL,
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"timer", &ckevt))
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pr_err("Failed to request irq %d (timer)\n", irq);
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clocksource_register_hz(&cksrc, rate);
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clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
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}
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static int __init mmp_dt_init_timer(struct device_node *np)
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{
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struct clk *clk;
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int irq, ret;
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unsigned long rate;
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clk = of_clk_get(np, 0);
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if (!IS_ERR(clk)) {
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ret = clk_prepare_enable(clk);
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if (ret)
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return ret;
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rate = clk_get_rate(clk);
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} else if (cpu_is_pj4()) {
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rate = 6500000;
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} else {
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rate = 3250000;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq)
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return -EINVAL;
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mmp_timer_base = of_iomap(np, 0);
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if (!mmp_timer_base)
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return -ENOMEM;
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mmp_timer_init(irq, rate);
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return 0;
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}
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TIMER_OF_DECLARE(mmp_timer, "mrvl,mmp-timer", mmp_dt_init_timer);
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