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On ppc64 we support 4K hash pte with 64K page size. That requires us to track the hash pte slot information on a per 4k basis. We do that by storing the slot details in the second half of pte page. The pte bit _PAGE_COMBO is used to indicate whether the second half need to be looked while building real_pte. We need to use read memory barrier while doing that so that load of hidx is not reordered w.r.t _PAGE_COMBO check. On the store side we already do a lwsync in __hash_page_4K CC: <stable@vger.kernel.org> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
103 lines
3.7 KiB
C
103 lines
3.7 KiB
C
/* To be include by pgtable-hash64.h only */
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/* Additional PTE bits (don't change without checking asm in hash_low.S) */
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#define _PAGE_SPECIAL 0x00000400 /* software: special page */
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#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
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#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
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#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
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#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
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/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
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* we set that to be the whole sub-bits mask. The C code will only
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* test this, so a multi-bit mask will work. For combo pages, this
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* is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
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* all the sub bits. For real 64k pages, we now have the assembly set
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* _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
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* that mask. This is fine as long as the HIDX bits are never set on
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* a PTE that isn't hashed, which is the case today.
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*
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* A little nit is for the huge page C code, which does the hashing
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* in C, we need to provide which bit to use.
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*/
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#define _PAGE_HASHPTE _PAGE_HPTE_SUB
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/* Note the full page bits must be in the same location as for normal
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* 4k pages as the same assembly will be used to insert 64K pages
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* whether the kernel has CONFIG_PPC_64K_PAGES or not
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*/
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#define _PAGE_F_SECOND 0x00008000 /* full page: hidx bits */
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#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
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/* PTE flags to conserve for HPTE identification */
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#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
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/* Shift to put page number into pte.
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*
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* That gives us a max RPN of 34 bits, which means a max of 50 bits
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* of addressable physical space, or 46 bits for the special 4k PFNs.
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*/
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#define PTE_RPN_SHIFT (30)
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#ifndef __ASSEMBLY__
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/*
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* With 64K pages on hash table, we have a special PTE format that
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* uses a second "half" of the page table to encode sub-page information
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* in order to deal with 64K made of 4K HW pages. Thus we override the
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* generic accessors and iterators here
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*/
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#define __real_pte __real_pte
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static inline real_pte_t __real_pte(pte_t pte, pte_t *ptep)
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{
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real_pte_t rpte;
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rpte.pte = pte;
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rpte.hidx = 0;
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if (pte_val(pte) & _PAGE_COMBO) {
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/*
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* Make sure we order the hidx load against the _PAGE_COMBO
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* check. The store side ordering is done in __hash_page_4K
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*/
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smp_rmb();
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rpte.hidx = pte_val(*((ptep) + PTRS_PER_PTE));
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}
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return rpte;
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}
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static inline unsigned long __rpte_to_hidx(real_pte_t rpte, unsigned long index)
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{
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if ((pte_val(rpte.pte) & _PAGE_COMBO))
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return (rpte.hidx >> (index<<2)) & 0xf;
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return (pte_val(rpte.pte) >> 12) & 0xf;
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}
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#define __rpte_to_pte(r) ((r).pte)
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#define __rpte_sub_valid(rpte, index) \
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(pte_val(rpte.pte) & (_PAGE_HPTE_SUB0 >> (index)))
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/* Trick: we set __end to va + 64k, which happens works for
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* a 16M page as well as we want only one iteration
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*/
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#define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \
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do { \
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unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT)); \
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unsigned __split = (psize == MMU_PAGE_4K || \
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psize == MMU_PAGE_64K_AP); \
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shift = mmu_psize_defs[psize].shift; \
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for (index = 0; vpn < __end; index++, \
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vpn += (1L << (shift - VPN_SHIFT))) { \
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if (!__split || __rpte_sub_valid(rpte, index)) \
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do {
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#define pte_iterate_hashed_end() } while(0); } } while(0)
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#define pte_pagesize_index(mm, addr, pte) \
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(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
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#define remap_4k_pfn(vma, addr, pfn, prot) \
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(WARN_ON(((pfn) >= (1UL << (64 - PTE_RPN_SHIFT)))) ? -EINVAL : \
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remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, \
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__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)))
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#endif /* __ASSEMBLY__ */
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