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The macrology in cmpxchg.h was designed to allow arbitrary pointer
and integer values to be passed through the routines. To support
cmpxchg() on 64-bit values on the 32-bit tilepro architecture, we
used the idiom "(typeof(val))(typeof(val-val))". This way, in the
"size 8" branch of the switch, when the underlying cmpxchg routine
returns a 64-bit quantity, we cast it first to a typeof(val-val)
quantity (i.e. size_t if "val" is a pointer) with no warnings about
casting between pointers and integers of different sizes, then cast
onwards to typeof(val), again with no warnings. If val is not a
pointer type, the additional cast is a no-op. We can't replace the
typeof(val-val) cast with (for example) unsigned long, since then if
"val" is really a 64-bit type, we cast away the high bits.
HOWEVER, this fails with current gcc (through 4.7 at least) if "val"
is a pointer to an incomplete type. Unfortunately gcc isn't smart
enough to realize that "val - val" will always be a size_t type
even if it's an incomplete type pointer.
Accordingly, I've reworked the way we handle the casting. We have
given up the ability to use cmpxchg() on 64-bit values on tilepro,
which is OK in the kernel since we should use cmpxchg64() explicitly
on such values anyway. As a result, I can just use simple "unsigned
long" casts internally.
As I reworked it, I realized it would be cleaner to move the
architecture-specific conditionals for cmpxchg and xchg out of the
atomic.h headers and into cmpxchg, and then use the cmpxchg() and
xchg() primitives directly in atomic.h and elsewhere. This allowed
the cmpxchg.h header to stand on its own without relying on the
implicit include of it that is performed by <asm/atomic.h>.
It also allowed collapsing the atomic_xchg/atomic_cmpxchg routines
from atomic_{32,64}.h into atomic.h.
I improved the tests that guard the allowed size of the arguments
to the routines to use a __compiletime_error() test. (By avoiding
the use of BUILD_BUG, I could include cmpxchg.h into bitops.h as
well and use the macros there, which is otherwise impossible due
to include order dependency issues.)
The tilepro _atomic_xxx internal methods were previously set up to
take atomic_t and atomic64_t arguments, which isn't as convenient
with the new model, so I modified them to take int or u64 arguments,
which is consistent with how they used the arguments internally
anyway, so provided some nice simplification there too.
Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
131 lines
4.1 KiB
C
131 lines
4.1 KiB
C
/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation, version 2.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
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* NON INFRINGEMENT. See the GNU General Public License for
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* more details.
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*/
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#ifndef _ASM_TILE_BITOPS_32_H
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#define _ASM_TILE_BITOPS_32_H
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#include <linux/compiler.h>
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#include <asm/barrier.h>
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/* Tile-specific routines to support <asm/bitops.h>. */
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unsigned long _atomic_or(volatile unsigned long *p, unsigned long mask);
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unsigned long _atomic_andn(volatile unsigned long *p, unsigned long mask);
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unsigned long _atomic_xor(volatile unsigned long *p, unsigned long mask);
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/**
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* set_bit - Atomically set a bit in memory
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* @nr: the bit to set
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* @addr: the address to start counting from
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*
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* This function is atomic and may not be reordered.
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* See __set_bit() if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void set_bit(unsigned nr, volatile unsigned long *addr)
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{
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_atomic_or(addr + BIT_WORD(nr), BIT_MASK(nr));
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}
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/**
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* clear_bit - Clears a bit in memory
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* @nr: Bit to clear
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* @addr: Address to start counting from
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*
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* clear_bit() is atomic and may not be reordered.
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* See __clear_bit() if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*
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* clear_bit() may not contain a memory barrier, so if it is used for
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* locking purposes, you should call smp_mb__before_clear_bit() and/or
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* smp_mb__after_clear_bit() to ensure changes are visible on other cpus.
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*/
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static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
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{
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_atomic_andn(addr + BIT_WORD(nr), BIT_MASK(nr));
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}
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/**
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* change_bit - Toggle a bit in memory
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* @nr: Bit to change
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* @addr: Address to start counting from
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*
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* change_bit() is atomic and may not be reordered.
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* See __change_bit() if you do not require the atomic guarantees.
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* Note that @nr may be almost arbitrarily large; this function is not
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* restricted to acting on a single-word quantity.
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*/
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static inline void change_bit(unsigned nr, volatile unsigned long *addr)
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{
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_atomic_xor(addr + BIT_WORD(nr), BIT_MASK(nr));
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}
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/**
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* test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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addr += BIT_WORD(nr);
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smp_mb(); /* barrier for proper semantics */
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return (_atomic_or(addr, mask) & mask) != 0;
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}
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/**
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* test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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addr += BIT_WORD(nr);
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smp_mb(); /* barrier for proper semantics */
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return (_atomic_andn(addr, mask) & mask) != 0;
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}
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/**
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* test_and_change_bit - Change a bit and return its old value
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* @nr: Bit to change
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* @addr: Address to count from
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*
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* This operation is atomic and cannot be reordered.
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* It also implies a memory barrier.
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*/
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static inline int test_and_change_bit(unsigned nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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addr += BIT_WORD(nr);
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smp_mb(); /* barrier for proper semantics */
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return (_atomic_xor(addr, mask) & mask) != 0;
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}
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/* See discussion at smp_mb__before_atomic_dec() in <asm/atomic_32.h>. */
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() do {} while (0)
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#include <asm-generic/bitops/ext2-atomic.h>
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#endif /* _ASM_TILE_BITOPS_32_H */
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