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2ce39ad151
Clearing PSTATE.D is one of the requirements for generating a debug
exception. The arm64 booting protocol requires that PSTATE.D is set,
since many of the debug registers (for example, the hw_breakpoint
registers) are UNKNOWN out of reset and could potentially generate
spurious, fatal debug exceptions in early boot code if PSTATE.D was
clear. Once the debug registers have been safely initialised, PSTATE.D
is cleared, however this is currently broken for two reasons:
(1) The boot CPU clears PSTATE.D in a postcore_initcall and secondary
CPUs clear PSTATE.D in secondary_start_kernel. Since the initcall
runs after SMP (and the scheduler) have been initialised, there is
no guarantee that it is actually running on the boot CPU. In this
case, the boot CPU is left with PSTATE.D set and is not capable of
generating debug exceptions.
(2) In a preemptible kernel, we may explicitly schedule on the IRQ
return path to EL1. If an IRQ occurs with PSTATE.D set in the idle
thread, then we may schedule the kthread_init thread, run the
postcore_initcall to clear PSTATE.D and then context switch back
to the idle thread before returning from the IRQ. The exception
return path will then restore PSTATE.D from the stack, and set it
again.
This patch fixes the problem by moving the clearing of PSTATE.D earlier
to proc.S. This has the desirable effect of clearing it in one place for
all CPUs, long before we have to worry about the scheduler or any
exception handling. We ensure that the previous reset of MDSCR_EL1 has
completed before unmasking the exception, so that any spurious
exceptions resulting from UNKNOWN debug registers are not generated.
Without this patch applied, the kprobes selftests have been seen to fail
under KVM, where we end up attempting to step the OOL instruction buffer
with PSTATE.D set and therefore fail to complete the step.
Cc: <stable@vger.kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
260 lines
6.0 KiB
ArmAsm
260 lines
6.0 KiB
ArmAsm
/*
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* Based on arch/arm/mm/proc.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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#ifdef CONFIG_ARM64_64K_PAGES
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#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
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#elif defined(CONFIG_ARM64_16K_PAGES)
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#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
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#else /* CONFIG_ARM64_4K_PAGES */
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#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
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#endif
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#define TCR_SMP_FLAGS TCR_SHARED
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/* PTWs cacheable, inner/outer WBWA */
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#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
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#define MAIR(attr, mt) ((attr) << ((mt) * 8))
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/*
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* cpu_do_idle()
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*
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* Idle the processor (wait for interrupt).
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*/
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ENTRY(cpu_do_idle)
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dsb sy // WFI may enter a low-power mode
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wfi
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ret
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ENDPROC(cpu_do_idle)
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#ifdef CONFIG_CPU_PM
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/**
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* cpu_do_suspend - save CPU registers context
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*
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* x0: virtual address of context pointer
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*/
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ENTRY(cpu_do_suspend)
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mrs x2, tpidr_el0
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mrs x3, tpidrro_el0
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mrs x4, contextidr_el1
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mrs x5, cpacr_el1
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mrs x6, tcr_el1
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mrs x7, vbar_el1
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mrs x8, mdscr_el1
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mrs x9, oslsr_el1
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mrs x10, sctlr_el1
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stp x2, x3, [x0]
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stp x4, xzr, [x0, #16]
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stp x5, x6, [x0, #32]
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stp x7, x8, [x0, #48]
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stp x9, x10, [x0, #64]
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ret
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ENDPROC(cpu_do_suspend)
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/**
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* cpu_do_resume - restore CPU register context
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*
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* x0: Address of context pointer
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*/
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ENTRY(cpu_do_resume)
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ldp x2, x3, [x0]
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ldp x4, x5, [x0, #16]
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ldp x6, x8, [x0, #32]
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ldp x9, x10, [x0, #48]
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ldp x11, x12, [x0, #64]
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msr tpidr_el0, x2
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msr tpidrro_el0, x3
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msr contextidr_el1, x4
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msr cpacr_el1, x6
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/* Don't change t0sz here, mask those bits when restoring */
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mrs x5, tcr_el1
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bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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msr tcr_el1, x8
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msr vbar_el1, x9
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msr mdscr_el1, x10
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msr sctlr_el1, x12
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/*
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* Restore oslsr_el1 by writing oslar_el1
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*/
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ubfx x11, x11, #1, #1
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msr oslar_el1, x11
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reset_pmuserenr_el0 x0 // Disable PMU access from EL0
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isb
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ret
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ENDPROC(cpu_do_resume)
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#endif
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/*
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* cpu_do_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys.
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*
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* - pgd_phys - physical address of new TTB
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*/
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ENTRY(cpu_do_switch_mm)
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mmid x1, x1 // get mm->context.id
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bfi x0, x1, #48, #16 // set the ASID
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msr ttbr0_el1, x0 // set TTBR0
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isb
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alternative_if_not ARM64_WORKAROUND_CAVIUM_27456
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ret
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nop
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nop
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nop
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alternative_else
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ic iallu
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dsb nsh
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isb
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ret
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alternative_endif
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ENDPROC(cpu_do_switch_mm)
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.pushsection ".idmap.text", "ax"
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/*
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* void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
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*
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* This is the low-level counterpart to cpu_replace_ttbr1, and should not be
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* called by anything else. It can only be executed from a TTBR0 mapping.
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*/
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ENTRY(idmap_cpu_replace_ttbr1)
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mrs x2, daif
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msr daifset, #0xf
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adrp x1, empty_zero_page
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msr ttbr1_el1, x1
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isb
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tlbi vmalle1
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dsb nsh
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isb
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msr ttbr1_el1, x0
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isb
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msr daif, x2
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ret
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ENDPROC(idmap_cpu_replace_ttbr1)
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.popsection
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/*
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* __cpu_setup
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*
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* Initialise the processor for turning the MMU on. Return in x0 the
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* value of the SCTLR_EL1 register.
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*/
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ENTRY(__cpu_setup)
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tlbi vmalle1 // Invalidate local TLB
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dsb nsh
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mov x0, #3 << 20
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msr cpacr_el1, x0 // Enable FP/ASIMD
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mov x0, #1 << 12 // Reset mdscr_el1 and disable
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msr mdscr_el1, x0 // access to the DCC from EL0
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isb // Unmask debug exceptions now,
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enable_dbg // since this is per-cpu
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reset_pmuserenr_el0 x0 // Disable PMU access from EL0
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/*
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* Memory region attributes for LPAE:
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*
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* n = AttrIndx[2:0]
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* n MAIR
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* DEVICE_nGnRnE 000 00000000
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* DEVICE_nGnRE 001 00000100
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* DEVICE_GRE 010 00001100
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* NORMAL_NC 011 01000100
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* NORMAL 100 11111111
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* NORMAL_WT 101 10111011
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*/
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ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
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MAIR(0x04, MT_DEVICE_nGnRE) | \
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MAIR(0x0c, MT_DEVICE_GRE) | \
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MAIR(0x44, MT_NORMAL_NC) | \
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MAIR(0xff, MT_NORMAL) | \
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MAIR(0xbb, MT_NORMAL_WT)
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msr mair_el1, x5
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/*
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* Prepare SCTLR
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*/
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adr x5, crval
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ldp w5, w6, [x5]
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mrs x0, sctlr_el1
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bic x0, x0, x5 // clear bits
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orr x0, x0, x6 // set bits
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/*
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* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
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* both user and kernel.
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*/
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ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
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TCR_TG_FLAGS | TCR_ASID16 | TCR_TBI0
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tcr_set_idmap_t0sz x10, x9
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/*
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* Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
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* TCR_EL1.
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*/
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mrs x9, ID_AA64MMFR0_EL1
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bfi x10, x9, #32, #3
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#ifdef CONFIG_ARM64_HW_AFDBM
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/*
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* Hardware update of the Access and Dirty bits.
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*/
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mrs x9, ID_AA64MMFR1_EL1
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and x9, x9, #0xf
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cbz x9, 2f
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cmp x9, #2
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b.lt 1f
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orr x10, x10, #TCR_HD // hardware Dirty flag update
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1: orr x10, x10, #TCR_HA // hardware Access flag update
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2:
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#endif /* CONFIG_ARM64_HW_AFDBM */
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msr tcr_el1, x10
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ret // return to head.S
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ENDPROC(__cpu_setup)
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/*
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* We set the desired value explicitly, including those of the
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* reserved bits. The values of bits EE & E0E were set early in
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* el2_setup, which are left untouched below.
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*
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* n n T
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* U E WT T UD US IHBS
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* CE0 XWHW CZ ME TEEA S
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* .... .IEE .... NEAI TE.I ..AD DEN0 ACAM
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* 0011 0... 1101 ..0. ..0. 10.. .0.. .... < hardware reserved
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* .... .1.. .... 01.1 11.1 ..01 0.01 1101 < software settings
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*/
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.type crval, #object
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crval:
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.word 0xfcffffff // clear
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.word 0x34d5d91d // set
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