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This adds basic CPU and cluster reset controls on RTSM for the A15x4-A7x4 model configuration using the Dual Cluster System Configuration Block (DCSCB). The cache coherency interconnect (CCI) is not handled yet. Signed-off-by: Nicolas Pitre <nico@linaro.org> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Pawel Moll <pawel.moll@arm.com>
20 lines
529 B
Plaintext
20 lines
529 B
Plaintext
ARM Dual Cluster System Configuration Block
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The Dual Cluster System Configuration Block (DCSCB) provides basic
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functionality for controlling clocks, resets and configuration pins in
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the Dual Cluster System implemented by the Real-Time System Model (RTSM).
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Required properties:
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- compatible : should be "arm,rtsm,dcscb"
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- reg : physical base address and the size of the registers window
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Example:
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dcscb@60000000 {
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compatible = "arm,rtsm,dcscb";
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reg = <0x60000000 0x1000>;
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};
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