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https://github.com/torvalds/linux.git
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6953af7749
This adds a macro used for defining address window's target ID and attribute cells for the MBus ranges entry. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
512 lines
10 KiB
Plaintext
512 lines
10 KiB
Plaintext
/include/ "skeleton.dtsi"
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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compatible = "marvell,dove";
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model = "Marvell Armada 88AP510 SoC";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "marvell,pj4a", "marvell,sheeva-v7";
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device_type = "cpu";
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next-level-cache = <&l2>;
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reg = <0>;
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};
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};
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l2: l2-cache {
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compatible = "marvell,tauros2-cache";
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marvell,tauros2-cache-features = <0>;
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};
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soc@f1000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges = <0xc8000000 0xc8000000 0x0100000 /* CESA SRAM 1M */
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0xe0000000 0xe0000000 0x8000000 /* PCIe0 Mem 128M */
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0xe8000000 0xe8000000 0x8000000 /* PCIe1 Mem 128M */
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0xf0000000 0xf0000000 0x0100000 /* ScratchPad 1M */
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0x00000000 0xf1000000 0x1000000 /* SB/NB regs 16M */
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0xf2000000 0xf2000000 0x0100000 /* PCIe0 I/O 1M */
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0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
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0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
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timer: timer@20300 {
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compatible = "marvell,orion-timer";
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reg = <0x20300 0x20>;
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interrupt-parent = <&bridge_intc>;
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interrupts = <1>, <2>;
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clocks = <&core_clk 0>;
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};
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intc: main-interrupt-ctrl@20200 {
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compatible = "marvell,orion-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20200 0x10>, <0x20210 0x10>;
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};
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bridge_intc: bridge-interrupt-ctrl@20110 {
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compatible = "marvell,orion-bridge-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x20110 0x8>;
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interrupts = <0>;
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marvell,#interrupts = <5>;
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};
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core_clk: core-clocks@d0214 {
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compatible = "marvell,dove-core-clock";
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reg = <0xd0214 0x4>;
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#clock-cells = <1>;
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};
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gate_clk: clock-gating-ctrl@d0038 {
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compatible = "marvell,dove-gating-clock";
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reg = <0xd0038 0x4>;
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clocks = <&core_clk 0>;
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#clock-cells = <1>;
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};
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thermal: thermal-diode@d001c {
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compatible = "marvell,dove-thermal";
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reg = <0xd001c 0x0c>, <0xd005c 0x08>;
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};
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uart0: serial@12000 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <7>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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uart1: serial@12100 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <8>;
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clocks = <&core_clk 0>;
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pinctrl-0 = <&pmx_uart1>;
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pinctrl-names = "default";
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status = "disabled";
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};
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uart2: serial@12200 {
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compatible = "ns16550a";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <9>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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uart3: serial@12300 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <10>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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gpio0: gpio-ctrl@d0400 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xd0400 0x20>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <12>, <13>, <14>, <60>;
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};
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gpio1: gpio-ctrl@d0420 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xd0420 0x20>;
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ngpios = <32>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <61>;
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};
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gpio2: gpio-ctrl@e8400 {
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compatible = "marvell,orion-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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reg = <0xe8400 0x0c>;
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ngpios = <8>;
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};
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pinctrl: pin-ctrl@d0200 {
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compatible = "marvell,dove-pinctrl";
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reg = <0xd0200 0x10>;
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clocks = <&gate_clk 22>;
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pmx_gpio_0: pmx-gpio-0 {
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marvell,pins = "mpp0";
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marvell,function = "gpio";
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};
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pmx_gpio_1: pmx-gpio-1 {
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marvell,pins = "mpp1";
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marvell,function = "gpio";
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};
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pmx_gpio_2: pmx-gpio-2 {
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marvell,pins = "mpp2";
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marvell,function = "gpio";
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};
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pmx_gpio_3: pmx-gpio-3 {
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marvell,pins = "mpp3";
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marvell,function = "gpio";
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};
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pmx_gpio_4: pmx-gpio-4 {
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marvell,pins = "mpp4";
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marvell,function = "gpio";
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};
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pmx_gpio_5: pmx-gpio-5 {
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marvell,pins = "mpp5";
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marvell,function = "gpio";
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};
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pmx_gpio_6: pmx-gpio-6 {
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marvell,pins = "mpp6";
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marvell,function = "gpio";
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};
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pmx_gpio_7: pmx-gpio-7 {
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marvell,pins = "mpp7";
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marvell,function = "gpio";
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};
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pmx_gpio_8: pmx-gpio-8 {
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marvell,pins = "mpp8";
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marvell,function = "gpio";
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};
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pmx_gpio_9: pmx-gpio-9 {
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marvell,pins = "mpp9";
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marvell,function = "gpio";
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};
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pmx_gpio_10: pmx-gpio-10 {
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marvell,pins = "mpp10";
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marvell,function = "gpio";
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};
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pmx_gpio_11: pmx-gpio-11 {
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marvell,pins = "mpp11";
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marvell,function = "gpio";
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};
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pmx_gpio_12: pmx-gpio-12 {
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marvell,pins = "mpp12";
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marvell,function = "gpio";
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};
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pmx_gpio_13: pmx-gpio-13 {
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marvell,pins = "mpp13";
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marvell,function = "gpio";
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};
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pmx_gpio_14: pmx-gpio-14 {
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marvell,pins = "mpp14";
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marvell,function = "gpio";
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};
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pmx_gpio_15: pmx-gpio-15 {
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marvell,pins = "mpp15";
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marvell,function = "gpio";
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};
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pmx_gpio_16: pmx-gpio-16 {
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marvell,pins = "mpp16";
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marvell,function = "gpio";
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};
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pmx_gpio_17: pmx-gpio-17 {
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marvell,pins = "mpp17";
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marvell,function = "gpio";
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};
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pmx_gpio_18: pmx-gpio-18 {
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marvell,pins = "mpp18";
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marvell,function = "gpio";
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};
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pmx_gpio_19: pmx-gpio-19 {
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marvell,pins = "mpp19";
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marvell,function = "gpio";
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};
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pmx_gpio_20: pmx-gpio-20 {
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marvell,pins = "mpp20";
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marvell,function = "gpio";
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};
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pmx_gpio_21: pmx-gpio-21 {
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marvell,pins = "mpp21";
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marvell,function = "gpio";
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};
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pmx_camera: pmx-camera {
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marvell,pins = "mpp_camera";
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marvell,function = "camera";
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};
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pmx_camera_gpio: pmx-camera-gpio {
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marvell,pins = "mpp_camera";
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marvell,function = "gpio";
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};
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pmx_sdio0: pmx-sdio0 {
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marvell,pins = "mpp_sdio0";
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marvell,function = "sdio0";
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};
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pmx_sdio0_gpio: pmx-sdio0-gpio {
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marvell,pins = "mpp_sdio0";
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marvell,function = "gpio";
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};
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pmx_sdio1: pmx-sdio1 {
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marvell,pins = "mpp_sdio1";
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marvell,function = "sdio1";
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};
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pmx_sdio1_gpio: pmx-sdio1-gpio {
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marvell,pins = "mpp_sdio1";
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marvell,function = "gpio";
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};
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pmx_audio1_gpio: pmx-audio1-gpio {
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marvell,pins = "mpp_audio1";
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marvell,function = "gpio";
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};
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pmx_spi0: pmx-spi0 {
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marvell,pins = "mpp_spi0";
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marvell,function = "spi0";
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};
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pmx_spi0_gpio: pmx-spi0-gpio {
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marvell,pins = "mpp_spi0";
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marvell,function = "gpio";
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};
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pmx_uart1: pmx-uart1 {
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marvell,pins = "mpp_uart1";
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marvell,function = "uart1";
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};
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pmx_uart1_gpio: pmx-uart1-gpio {
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marvell,pins = "mpp_uart1";
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marvell,function = "gpio";
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};
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pmx_nand: pmx-nand {
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marvell,pins = "mpp_nand";
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marvell,function = "nand";
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};
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pmx_nand_gpo: pmx-nand-gpo {
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marvell,pins = "mpp_nand";
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marvell,function = "gpo";
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};
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};
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spi0: spi-ctrl@10600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <6>;
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reg = <0x10600 0x28>;
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clocks = <&core_clk 0>;
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pinctrl-0 = <&pmx_spi0>;
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pinctrl-names = "default";
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status = "disabled";
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};
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spi1: spi-ctrl@14600 {
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compatible = "marvell,orion-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <5>;
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reg = <0x14600 0x28>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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i2c0: i2c-ctrl@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <11>;
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clock-frequency = <400000>;
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timeout-ms = <1000>;
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clocks = <&core_clk 0>;
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status = "disabled";
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};
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ehci0: usb-host@50000 {
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compatible = "marvell,orion-ehci";
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reg = <0x50000 0x1000>;
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interrupts = <24>;
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clocks = <&gate_clk 0>;
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status = "okay";
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};
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ehci1: usb-host@51000 {
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compatible = "marvell,orion-ehci";
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reg = <0x51000 0x1000>;
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interrupts = <25>;
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clocks = <&gate_clk 1>;
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status = "okay";
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};
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sdio0: sdio-host@92000 {
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compatible = "marvell,dove-sdhci";
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reg = <0x92000 0x100>;
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interrupts = <35>, <37>;
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clocks = <&gate_clk 8>;
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pinctrl-0 = <&pmx_sdio0>;
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pinctrl-names = "default";
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status = "disabled";
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};
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sdio1: sdio-host@90000 {
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compatible = "marvell,dove-sdhci";
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reg = <0x90000 0x100>;
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interrupts = <36>, <38>;
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clocks = <&gate_clk 9>;
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pinctrl-0 = <&pmx_sdio1>;
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pinctrl-names = "default";
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status = "disabled";
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};
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sata0: sata-host@a0000 {
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compatible = "marvell,orion-sata";
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reg = <0xa0000 0x2400>;
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interrupts = <62>;
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clocks = <&gate_clk 3>;
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nr-ports = <1>;
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status = "disabled";
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};
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rtc: real-time-clock@d8500 {
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compatible = "marvell,orion-rtc";
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reg = <0xd8500 0x20>;
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};
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crypto: crypto-engine@30000 {
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compatible = "marvell,orion-crypto";
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reg = <0x30000 0x10000>,
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<0xc8000000 0x800>;
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reg-names = "regs", "sram";
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interrupts = <31>;
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clocks = <&gate_clk 15>;
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status = "okay";
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};
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xor0: dma-engine@60800 {
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compatible = "marvell,orion-xor";
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reg = <0x60800 0x100
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0x60a00 0x100>;
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clocks = <&gate_clk 23>;
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status = "okay";
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channel0 {
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interrupts = <39>;
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dmacap,memcpy;
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dmacap,xor;
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};
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channel1 {
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interrupts = <40>;
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dmacap,memset;
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dmacap,memcpy;
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dmacap,xor;
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};
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};
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xor1: dma-engine@60900 {
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compatible = "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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clocks = <&gate_clk 24>;
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status = "okay";
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channel0 {
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interrupts = <42>;
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dmacap,memcpy;
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dmacap,xor;
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};
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channel1 {
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interrupts = <43>;
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dmacap,memset;
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dmacap,memcpy;
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dmacap,xor;
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};
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};
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mdio: mdio-bus@72004 {
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compatible = "marvell,orion-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x72004 0x84>;
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interrupts = <30>;
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clocks = <&gate_clk 2>;
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status = "disabled";
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ethphy: ethernet-phy {
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device-type = "ethernet-phy";
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/* set phy address in board file */
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};
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};
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eth: ethernet-controller@72000 {
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compatible = "marvell,orion-eth";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x72000 0x4000>;
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clocks = <&gate_clk 2>;
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marvell,tx-checksum-limit = <1600>;
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status = "disabled";
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ethernet-port@0 {
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device_type = "network";
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compatible = "marvell,orion-eth-port";
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reg = <0>;
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interrupts = <29>;
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/* overwrite MAC address in bootloader */
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local-mac-address = [00 00 00 00 00 00];
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phy-handle = <ðphy>;
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};
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};
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};
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};
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