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030761e097
The hardware has a set of '_NEXT' registers that can hold a second job while the first is executing. Make use of these registers to enqueue a second job per slot. v5: * Fix a comment in panfrost_job_init() v3: * Fix the done/err job dequeuing logic to get a valid active state * Only enable the second slot on GPUs supporting jobchain disambiguation * Split interrupt handling in sub-functions Signed-off-by: Steven Price <steven.price@arm.com> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Steven Price <steven.price@arm.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210630062751.2832545-16-boris.brezillon@collabora.com
266 lines
7.7 KiB
C
266 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright 2018 Marty E. Plummer <hanetzer@startmail.com> */
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/* Copyright 2019 Linaro, Ltd, Rob Herring <robh@kernel.org> */
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#ifndef __PANFROST_DEVICE_H__
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#define __PANFROST_DEVICE_H__
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#include <linux/atomic.h>
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#include <linux/io-pgtable.h>
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#include <linux/regulator/consumer.h>
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#include <linux/spinlock.h>
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#include <drm/drm_device.h>
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#include <drm/drm_mm.h>
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#include <drm/gpu_scheduler.h>
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#include "panfrost_devfreq.h"
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struct panfrost_device;
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struct panfrost_mmu;
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struct panfrost_job_slot;
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struct panfrost_job;
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struct panfrost_perfcnt;
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#define NUM_JOB_SLOTS 3
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#define MAX_PM_DOMAINS 3
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struct panfrost_features {
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u16 id;
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u16 revision;
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u64 shader_present;
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u64 tiler_present;
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u64 l2_present;
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u64 stack_present;
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u32 as_present;
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u32 js_present;
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u32 l2_features;
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u32 core_features;
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u32 tiler_features;
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u32 mem_features;
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u32 mmu_features;
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u32 thread_features;
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u32 max_threads;
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u32 thread_max_workgroup_sz;
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u32 thread_max_barrier_sz;
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u32 coherency_features;
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u32 afbc_features;
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u32 texture_features[4];
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u32 js_features[16];
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u32 nr_core_groups;
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u32 thread_tls_alloc;
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unsigned long hw_features[64 / BITS_PER_LONG];
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unsigned long hw_issues[64 / BITS_PER_LONG];
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};
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/*
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* Features that cannot be automatically detected and need matching using the
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* compatible string, typically SoC-specific.
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*/
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struct panfrost_compatible {
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/* Supplies count and names. */
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int num_supplies;
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const char * const *supply_names;
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/*
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* Number of power domains required, note that values 0 and 1 are
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* handled identically, as only values > 1 need special handling.
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*/
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int num_pm_domains;
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/* Only required if num_pm_domains > 1. */
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const char * const *pm_domain_names;
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/* Vendor implementation quirks callback */
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void (*vendor_quirk)(struct panfrost_device *pfdev);
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};
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struct panfrost_device {
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struct device *dev;
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struct drm_device *ddev;
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struct platform_device *pdev;
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void __iomem *iomem;
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struct clk *clock;
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struct clk *bus_clock;
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struct regulator_bulk_data *regulators;
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struct reset_control *rstc;
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/* pm_domains for devices with more than one. */
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struct device *pm_domain_devs[MAX_PM_DOMAINS];
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struct device_link *pm_domain_links[MAX_PM_DOMAINS];
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bool coherent;
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struct panfrost_features features;
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const struct panfrost_compatible *comp;
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spinlock_t as_lock;
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unsigned long as_in_use_mask;
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unsigned long as_alloc_mask;
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unsigned long as_faulty_mask;
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struct list_head as_lru_list;
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struct panfrost_job_slot *js;
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struct panfrost_job *jobs[NUM_JOB_SLOTS][2];
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struct list_head scheduled_jobs;
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struct panfrost_perfcnt *perfcnt;
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struct mutex sched_lock;
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struct {
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struct workqueue_struct *wq;
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struct work_struct work;
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atomic_t pending;
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} reset;
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struct mutex shrinker_lock;
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struct list_head shrinker_list;
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struct shrinker shrinker;
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struct panfrost_devfreq pfdevfreq;
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};
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struct panfrost_mmu {
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struct panfrost_device *pfdev;
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struct kref refcount;
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struct io_pgtable_cfg pgtbl_cfg;
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struct io_pgtable_ops *pgtbl_ops;
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struct drm_mm mm;
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spinlock_t mm_lock;
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int as;
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atomic_t as_count;
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struct list_head list;
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};
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struct panfrost_file_priv {
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struct panfrost_device *pfdev;
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struct drm_sched_entity sched_entity[NUM_JOB_SLOTS];
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struct panfrost_mmu *mmu;
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};
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static inline struct panfrost_device *to_panfrost_device(struct drm_device *ddev)
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{
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return ddev->dev_private;
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}
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static inline int panfrost_model_cmp(struct panfrost_device *pfdev, s32 id)
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{
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s32 match_id = pfdev->features.id;
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if (match_id & 0xf000)
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match_id &= 0xf00f;
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return match_id - id;
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}
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static inline bool panfrost_model_is_bifrost(struct panfrost_device *pfdev)
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{
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return panfrost_model_cmp(pfdev, 0x1000) >= 0;
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}
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static inline bool panfrost_model_eq(struct panfrost_device *pfdev, s32 id)
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{
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return !panfrost_model_cmp(pfdev, id);
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}
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int panfrost_unstable_ioctl_check(void);
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int panfrost_device_init(struct panfrost_device *pfdev);
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void panfrost_device_fini(struct panfrost_device *pfdev);
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void panfrost_device_reset(struct panfrost_device *pfdev);
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int panfrost_device_resume(struct device *dev);
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int panfrost_device_suspend(struct device *dev);
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enum drm_panfrost_exception_type {
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DRM_PANFROST_EXCEPTION_OK = 0x00,
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DRM_PANFROST_EXCEPTION_DONE = 0x01,
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DRM_PANFROST_EXCEPTION_INTERRUPTED = 0x02,
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DRM_PANFROST_EXCEPTION_STOPPED = 0x03,
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DRM_PANFROST_EXCEPTION_TERMINATED = 0x04,
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DRM_PANFROST_EXCEPTION_KABOOM = 0x05,
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DRM_PANFROST_EXCEPTION_EUREKA = 0x06,
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DRM_PANFROST_EXCEPTION_ACTIVE = 0x08,
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DRM_PANFROST_EXCEPTION_MAX_NON_FAULT = 0x3f,
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DRM_PANFROST_EXCEPTION_JOB_CONFIG_FAULT = 0x40,
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DRM_PANFROST_EXCEPTION_JOB_POWER_FAULT = 0x41,
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DRM_PANFROST_EXCEPTION_JOB_READ_FAULT = 0x42,
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DRM_PANFROST_EXCEPTION_JOB_WRITE_FAULT = 0x43,
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DRM_PANFROST_EXCEPTION_JOB_AFFINITY_FAULT = 0x44,
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DRM_PANFROST_EXCEPTION_JOB_BUS_FAULT = 0x48,
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DRM_PANFROST_EXCEPTION_INSTR_INVALID_PC = 0x50,
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DRM_PANFROST_EXCEPTION_INSTR_INVALID_ENC = 0x51,
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DRM_PANFROST_EXCEPTION_INSTR_TYPE_MISMATCH = 0x52,
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DRM_PANFROST_EXCEPTION_INSTR_OPERAND_FAULT = 0x53,
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DRM_PANFROST_EXCEPTION_INSTR_TLS_FAULT = 0x54,
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DRM_PANFROST_EXCEPTION_INSTR_BARRIER_FAULT = 0x55,
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DRM_PANFROST_EXCEPTION_INSTR_ALIGN_FAULT = 0x56,
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DRM_PANFROST_EXCEPTION_DATA_INVALID_FAULT = 0x58,
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DRM_PANFROST_EXCEPTION_TILE_RANGE_FAULT = 0x59,
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DRM_PANFROST_EXCEPTION_ADDR_RANGE_FAULT = 0x5a,
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DRM_PANFROST_EXCEPTION_IMPRECISE_FAULT = 0x5b,
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DRM_PANFROST_EXCEPTION_OOM = 0x60,
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DRM_PANFROST_EXCEPTION_OOM_AFBC = 0x61,
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DRM_PANFROST_EXCEPTION_UNKNOWN = 0x7f,
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DRM_PANFROST_EXCEPTION_DELAYED_BUS_FAULT = 0x80,
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DRM_PANFROST_EXCEPTION_GPU_SHAREABILITY_FAULT = 0x88,
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DRM_PANFROST_EXCEPTION_SYS_SHAREABILITY_FAULT = 0x89,
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DRM_PANFROST_EXCEPTION_GPU_CACHEABILITY_FAULT = 0x8a,
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DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_0 = 0xc0,
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DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_1 = 0xc1,
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DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_2 = 0xc2,
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DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_3 = 0xc3,
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DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_4 = 0xc4,
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DRM_PANFROST_EXCEPTION_TRANSLATION_FAULT_IDENTITY = 0xc7,
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DRM_PANFROST_EXCEPTION_PERM_FAULT_0 = 0xc8,
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DRM_PANFROST_EXCEPTION_PERM_FAULT_1 = 0xc9,
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DRM_PANFROST_EXCEPTION_PERM_FAULT_2 = 0xca,
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DRM_PANFROST_EXCEPTION_PERM_FAULT_3 = 0xcb,
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DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_0 = 0xd0,
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DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_1 = 0xd1,
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DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_2 = 0xd2,
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DRM_PANFROST_EXCEPTION_TRANSTAB_BUS_FAULT_3 = 0xd3,
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DRM_PANFROST_EXCEPTION_ACCESS_FLAG_0 = 0xd8,
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DRM_PANFROST_EXCEPTION_ACCESS_FLAG_1 = 0xd9,
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DRM_PANFROST_EXCEPTION_ACCESS_FLAG_2 = 0xda,
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DRM_PANFROST_EXCEPTION_ACCESS_FLAG_3 = 0xdb,
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DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN0 = 0xe0,
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DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN1 = 0xe1,
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DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN2 = 0xe2,
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DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_IN3 = 0xe3,
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DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT0 = 0xe4,
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DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT1 = 0xe5,
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DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT2 = 0xe6,
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DRM_PANFROST_EXCEPTION_ADDR_SIZE_FAULT_OUT3 = 0xe7,
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DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_0 = 0xe8,
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DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_1 = 0xe9,
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DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_2 = 0xea,
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DRM_PANFROST_EXCEPTION_MEM_ATTR_FAULT_3 = 0xeb,
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DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_0 = 0xec,
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DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_1 = 0xed,
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DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_2 = 0xee,
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DRM_PANFROST_EXCEPTION_MEM_ATTR_NONCACHE_3 = 0xef,
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};
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static inline bool
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panfrost_exception_is_fault(u32 exception_code)
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{
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return exception_code > DRM_PANFROST_EXCEPTION_MAX_NON_FAULT;
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}
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const char *panfrost_exception_name(u32 exception_code);
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bool panfrost_exception_needs_reset(const struct panfrost_device *pfdev,
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u32 exception_code);
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static inline void
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panfrost_device_schedule_reset(struct panfrost_device *pfdev)
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{
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atomic_set(&pfdev->reset.pending, 1);
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queue_work(pfdev->reset.wq, &pfdev->reset.work);
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}
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#endif
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