Zhiwu Song 684f741446 ARM: CSR: add rtc i/o bridge interface for SiRFprimaII ... The module is a bridge between the RTC clock domain and the CPU interface clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through this module. Signed-off-by: Zhiwu Song <zhiwu.song@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Arnd Bergmann <arnd@arndb.de>		2011-09-11 09:17:53 +08:00
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include/mach
clock.c	ARM: CSR: add missing sentinels to of_device_id tables	2011-09-11 09:11:26 +08:00
common.h
irq.c	ARM: CSR: IRQ: add simple irq_domain so that hw irq can map to Linux	2011-09-11 09:15:09 +08:00
l2x0.c	ARM: CSR: initializing L2 cache	2011-07-09 07:21:53 +08:00
lluart.c
Makefile	ARM: CSR: add rtc i/o bridge interface for SiRFprimaII	2011-09-11 09:17:53 +08:00
Makefile.boot
prima2.c
rstc.c	ARM: CSR: add missing sentinels to of_device_id tables	2011-09-11 09:11:26 +08:00
rtciobrg.c	ARM: CSR: add rtc i/o bridge interface for SiRFprimaII	2011-09-11 09:17:53 +08:00
timer.c	ARM: CSR: add missing sentinels to of_device_id tables	2011-09-11 09:11:26 +08:00