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301bcfac42
The ARM errata 819472, 826319, 827319 and 824069 define the same workaround for these hardware issues in certain Cortex-A53 parts. Use the new alternatives framework and the CPU MIDR detection to patch "cache clean" into "cache clean and invalidate" instructions if an affected CPU is detected at runtime. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [will: add __maybe_unused to squash gcc warning] Signed-off-by: Will Deacon <will.deacon@arm.com>
30 lines
671 B
C
30 lines
671 B
C
#ifndef __ASM_ALTERNATIVE_ASM_H
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#define __ASM_ALTERNATIVE_ASM_H
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#ifdef __ASSEMBLY__
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.macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len
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.word \orig_offset - .
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.word \alt_offset - .
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.hword \feature
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.byte \orig_len
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.byte \alt_len
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.endm
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.macro alternative_insn insn1 insn2 cap
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661: \insn1
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662: .pushsection .altinstructions, "a"
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altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f
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.popsection
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.pushsection .altinstr_replacement, "ax"
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663: \insn2
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664: .popsection
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.if ((664b-663b) != (662b-661b))
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.error "Alternatives instruction length mismatch"
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.endif
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ALTERNATIVE_ASM_H */
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