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67a57be85e
Enable pinctrl for Broadcom Capri (BCM281xx) SoCs. Signed-off-by: Sherman Yin <syin@broadcom.com> Reviewed-by: Christian Daudt <bcm@fixthebug.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
150 lines
3.7 KiB
Plaintext
150 lines
3.7 KiB
Plaintext
/*
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* Copyright (C) 2012-2013 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include "skeleton.dtsi"
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/ {
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model = "BCM11351 SoC";
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compatible = "brcm,bcm11351";
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interrupt-parent = <&gic>;
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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gic: interrupt-controller@3ff00100 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x3ff01000 0x1000>,
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<0x3ff00100 0x100>;
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};
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smc@0x3404c000 {
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compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
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reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
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};
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uart@3e000000 {
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compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e000000 0x1000>;
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clock-frequency = <13000000>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@3e001000 {
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compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e001000 0x1000>;
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clock-frequency = <13000000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@3e002000 {
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compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e002000 0x1000>;
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clock-frequency = <13000000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@3e003000 {
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compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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status = "disabled";
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reg = <0x3e003000 0x1000>;
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clock-frequency = <13000000>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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L2: l2-cache {
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compatible = "brcm,bcm11351-a2-pl310-cache";
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reg = <0x3ff20000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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watchdog@35002f40 {
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compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
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reg = <0x35002f40 0x6c>;
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};
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timer@35006000 {
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compatible = "brcm,kona-timer";
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reg = <0x35006000 0x1000>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <32768>;
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};
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gpio: gpio@35003000 {
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compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
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reg = <0x35003000 0x800>;
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interrupts =
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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gpio-controller;
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interrupt-controller;
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};
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sdio1: sdio@3f180000 {
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compatible = "brcm,kona-sdhci";
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reg = <0x3f180000 0x10000>;
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interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sdio2: sdio@3f190000 {
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compatible = "brcm,kona-sdhci";
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reg = <0x3f190000 0x10000>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sdio3: sdio@3f1a0000 {
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compatible = "brcm,kona-sdhci";
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reg = <0x3f1a0000 0x10000>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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sdio4: sdio@3f1b0000 {
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compatible = "brcm,kona-sdhci";
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reg = <0x3f1b0000 0x10000>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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pinctrl@35004800 {
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compatible = "brcm,capri-pinctrl";
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reg = <0x35004800 0x430>;
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};
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};
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