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901bdf5ea1
amd-drm-next-6.5-2023-06-02: amdgpu: - SR-IOV fixes - Warning fixes - Misc code cleanups and spelling fixes - DCN 3.2 updates - Improved DC FAMS support for better power management - Improved DC SubVP support for better power management - DCN 3.1.x fixes - Max IB size query - DC GPU reset fixes - RAS updates - DCN 3.0.x fixes - S/G display fixes - CP shadow buffer support - Implement connector force callback - Z8 power improvements - PSP 13.0.10 vbflash support - Mode2 reset fixes - Store MQDs in VRAM to improve queue switch latency - VCN 3.x fixes - JPEG 3.x fixes - Enable DC_FP on LoongArch - GFXOFF fixes - GC 9.4.3 partition support - SDMA 4.4.2 partition support - VCN/JPEG 4.0.3 partition support - VCN 4.0.3 updates - NBIO 7.9 updates - GC 9.4.3 updates - Take NUMA into account when allocating memory - Handle NUMA for partitions - SMU 13.0.6 updates - GC 9.4.3 RAS updates - Stop including unused swiotlb.h - SMU 13.0.7 fixes - Fix clock output ordering on some APUs - Clean up DC FPGA code - GFX9 preemption fixes - Misc irq fixes - S0ix fixes - Add new DRM_AMDGPU_WERROR config parameter to help with CI - PCIe fix for RDNA2 - kdoc fixes - Documentation updates amdkfd: - Query TTM mem limit rather than hardcoding it - GC 9.4.3 partition support - Handle NUMA for partitions radeon: - Fix possible double free - Stop including unused swiotlb.h - Fix possible division by zero ttm: - Add query for TTM mem limit - Add NUMA awareness to pools - Export ttm_pool_fini() UAPI: - Add new ctx query flag to better handle GPU resets Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290 - Add new interface to query and set shadow buffer for RDNA3 Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986 - Add new INFO query for max IB size Proposed userspace: https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3 amd-drm-next-6.5-2023-06-09: amdgpu: - S0ix fixes - Initial SMU13 Overdrive support - kdoc fixes - Misc clode cleanups - Flexible array fixes - Display OTG fixes - SMU 13.0.6 updates - Revert some broken clock counter updates - Misc display fixes - GFX9 preemption fixes - Add support for newer EEPROM bad page table format - Add missing radeon secondary id - Add support for new colorspace KMS API - CSA fix - Stable pstate fixes for APUs - make vbl interface admin only - Handle PCI accelerator class amdkfd: - Add debugger support for gdb radeon: - Fix possible UAF drm: - Add Colorspace functionality UAPI: - Add debugger interface for enabling gdb Proposed userspace: https://github.com/ROCm-Developer-Tools/ROCdbgapi/tree/wip-dbgapi - Add KMS colorspace API Discussion: https://lists.freedesktop.org/archives/dri-devel/2023-June/408128.html From: Alex Deucher <alexander.deucher@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609174817.7764-1-alexander.deucher@amd.com
95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright 2020 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Christian König
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*/
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#ifndef _TTM_PAGE_POOL_H_
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#define _TTM_PAGE_POOL_H_
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#include <linux/mmzone.h>
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#include <linux/llist.h>
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#include <linux/spinlock.h>
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#include <drm/ttm/ttm_caching.h>
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struct device;
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struct ttm_tt;
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struct ttm_pool;
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struct ttm_operation_ctx;
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/**
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* struct ttm_pool_type - Pool for a certain memory type
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*
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* @pool: the pool we belong to, might be NULL for the global ones
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* @order: the allocation order our pages have
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* @caching: the caching type our pages have
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* @shrinker_list: our place on the global shrinker list
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* @lock: protection of the page list
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* @pages: the list of pages in the pool
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*/
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struct ttm_pool_type {
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struct ttm_pool *pool;
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unsigned int order;
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enum ttm_caching caching;
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struct list_head shrinker_list;
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spinlock_t lock;
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struct list_head pages;
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};
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/**
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* struct ttm_pool - Pool for all caching and orders
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*
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* @dev: the device we allocate pages for
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* @nid: which numa node to use
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* @use_dma_alloc: if coherent DMA allocations should be used
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* @use_dma32: if GFP_DMA32 should be used
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* @caching: pools for each caching/order
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*/
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struct ttm_pool {
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struct device *dev;
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int nid;
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bool use_dma_alloc;
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bool use_dma32;
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struct {
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struct ttm_pool_type orders[MAX_ORDER + 1];
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} caching[TTM_NUM_CACHING_TYPES];
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};
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int ttm_pool_alloc(struct ttm_pool *pool, struct ttm_tt *tt,
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struct ttm_operation_ctx *ctx);
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void ttm_pool_free(struct ttm_pool *pool, struct ttm_tt *tt);
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void ttm_pool_init(struct ttm_pool *pool, struct device *dev,
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int nid, bool use_dma_alloc, bool use_dma32);
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void ttm_pool_fini(struct ttm_pool *pool);
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int ttm_pool_debugfs(struct ttm_pool *pool, struct seq_file *m);
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int ttm_pool_mgr_init(unsigned long num_pages);
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void ttm_pool_mgr_fini(void);
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#endif
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