mirror of
https://github.com/torvalds/linux.git
synced 2024-12-23 11:21:33 +00:00
b39cb1052a
Create the /sys/bus/cxl hierarchy to enumerate: * Memory Devices (per-endpoint control devices) * Memory Address Space Devices (platform address ranges with interleaving, performance, and persistence attributes) * Memory Regions (active provisioned memory from an address space device that is in use as System RAM or delegated to libnvdimm as Persistent Memory regions). For now, only the per-endpoint control devices are registered on the 'cxl' bus. However, going forward it will provide a mechanism to coordinate cross-device interleave. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> (v2) Link: https://lore.kernel.org/r/20210217040958.1354670-4-ben.widawsky@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
30 lines
620 B
C
30 lines
620 B
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
|
|
#include <linux/device.h>
|
|
#include <linux/module.h>
|
|
|
|
/**
|
|
* DOC: cxl bus
|
|
*
|
|
* The CXL bus provides namespace for control devices and a rendezvous
|
|
* point for cross-device interleave coordination.
|
|
*/
|
|
struct bus_type cxl_bus_type = {
|
|
.name = "cxl",
|
|
};
|
|
EXPORT_SYMBOL_GPL(cxl_bus_type);
|
|
|
|
static __init int cxl_bus_init(void)
|
|
{
|
|
return bus_register(&cxl_bus_type);
|
|
}
|
|
|
|
static void cxl_bus_exit(void)
|
|
{
|
|
bus_unregister(&cxl_bus_type);
|
|
}
|
|
|
|
module_init(cxl_bus_init);
|
|
module_exit(cxl_bus_exit);
|
|
MODULE_LICENSE("GPL v2");
|