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Implement the infrastructure for a simple bitmap based allocator, which will replace the x86 vector allocator. It's in the core code as other architectures might be able to reuse/extend it. For now it only implements allocations for single CPUs, but it's simple to add multi CPU allocation support if required. The concept is rather simple: Global information: system_vector bitmap global accounting PerCPU information: allocation bitmap managed allocation bitmap local accounting The system vector bitmap is used to exclude vectors system wide from the allocation space. The allocation bitmap is used to keep track of per cpu used vectors. The managed allocation bitmap is used to reserve vectors for managed interrupts. When a regular (non managed) interrupt allocation happens then the following rule applies: tmpmap = system_map | alloc_map | managed_map find_zero_bit(tmpmap) Oring the bitmaps together gives the real available space. The same rule applies for reserving a managed interrupt vector. But contrary to the regular interrupts the reservation only marks the bit in the managed map and therefor excludes it from the regular allocations. The managed map is only cleaned out when the a managed interrupt is completely released and it stays alive accross CPU offline/online operations. For managed interrupt allocations the rule is: tmpmap = managed_map & ~alloc_map find_first_bit(tmpmap) This returns the first bit which is in the managed map, but not yet allocated in the allocation map. The allocation marks it in the allocation map and hands it back to the caller for use. The rest of the code are helper functions to handle the various requirements and the accounting which are necessary to replace the x86 vector allocation code. The result is a single patch as the evolution of this infrastructure cannot be represented in bits and pieces. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Juergen Gross <jgross@suse.com> Tested-by: Yu Chen <yu.c.chen@intel.com> Acked-by: Juergen Gross <jgross@suse.com> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com> Cc: Tony Luck <tony.luck@intel.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Alok Kataria <akataria@vmware.com> Cc: Joerg Roedel <joro@8bytes.org> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Christoph Hellwig <hch@lst.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Rui Zhang <rui.zhang@intel.com> Cc: "K. Y. Srinivasan" <kys@microsoft.com> Cc: Arjan van de Ven <arjan@linux.intel.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: Chris Metcalf <cmetcalf@mellanox.com> Cc: Len Brown <lenb@kernel.org> Link: https://lkml.kernel.org/r/20170913213153.185437174@linutronix.de
142 lines
3.2 KiB
Plaintext
142 lines
3.2 KiB
Plaintext
menu "IRQ subsystem"
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# Options selectable by the architecture code
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# Make sparse irq Kconfig switch below available
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config MAY_HAVE_SPARSE_IRQ
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bool
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# Legacy support, required for itanic
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config GENERIC_IRQ_LEGACY
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bool
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# Enable the generic irq autoprobe mechanism
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config GENERIC_IRQ_PROBE
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bool
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# Use the generic /proc/interrupts implementation
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config GENERIC_IRQ_SHOW
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bool
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# Print level/edge extra information
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config GENERIC_IRQ_SHOW_LEVEL
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bool
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# Supports effective affinity mask
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config GENERIC_IRQ_EFFECTIVE_AFF_MASK
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bool
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# Facility to allocate a hardware interrupt. This is legacy support
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# and should not be used in new code. Use irq domains instead.
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config GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
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bool
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# Support for delayed migration from interrupt context
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config GENERIC_PENDING_IRQ
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bool
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# Support for generic irq migrating off cpu before the cpu is offline.
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config GENERIC_IRQ_MIGRATION
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bool
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# Alpha specific irq affinity mechanism
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config AUTO_IRQ_AFFINITY
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bool
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# Tasklet based software resend for pending interrupts on enable_irq()
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config HARDIRQS_SW_RESEND
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bool
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# Preflow handler support for fasteoi (sparc64)
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config IRQ_PREFLOW_FASTEOI
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bool
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# Edge style eoi based handler (cell)
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config IRQ_EDGE_EOI_HANDLER
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bool
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# Generic configurable interrupt chip implementation
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config GENERIC_IRQ_CHIP
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bool
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select IRQ_DOMAIN
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# Generic irq_domain hw <--> linux irq number translation
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config IRQ_DOMAIN
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bool
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# Support for simulated interrupts
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config IRQ_SIM
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bool
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select IRQ_WORK
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# Support for hierarchical irq domains
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config IRQ_DOMAIN_HIERARCHY
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bool
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select IRQ_DOMAIN
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# Support for hierarchical fasteoi+edge and fasteoi+level handlers
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config IRQ_FASTEOI_HIERARCHY_HANDLERS
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bool
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# Generic IRQ IPI support
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config GENERIC_IRQ_IPI
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bool
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# Generic MSI interrupt support
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config GENERIC_MSI_IRQ
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bool
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# Generic MSI hierarchical interrupt domain support
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config GENERIC_MSI_IRQ_DOMAIN
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bool
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select IRQ_DOMAIN_HIERARCHY
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select GENERIC_MSI_IRQ
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config HANDLE_DOMAIN_IRQ
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bool
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config IRQ_TIMINGS
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bool
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config GENERIC_IRQ_MATRIX_ALLOCATOR
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bool
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config IRQ_DOMAIN_DEBUG
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bool "Expose hardware/virtual IRQ mapping via debugfs"
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depends on IRQ_DOMAIN && DEBUG_FS
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help
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This option will show the mapping relationship between hardware irq
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numbers and Linux irq numbers. The mapping is exposed via debugfs
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in the file "irq_domain_mapping".
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If you don't know what this means you don't need it.
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# Support forced irq threading
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config IRQ_FORCED_THREADING
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bool
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config SPARSE_IRQ
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bool "Support sparse irq numbering" if MAY_HAVE_SPARSE_IRQ
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---help---
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Sparse irq numbering is useful for distro kernels that want
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to define a high CONFIG_NR_CPUS value but still want to have
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low kernel memory footprint on smaller machines.
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( Sparse irqs can also be beneficial on NUMA boxes, as they spread
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out the interrupt descriptors in a more NUMA-friendly way. )
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If you don't know what to do here, say N.
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config GENERIC_IRQ_DEBUGFS
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bool "Expose irq internals in debugfs"
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depends on DEBUG_FS
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default n
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---help---
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Exposes internal state information through debugfs. Mostly for
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developers and debugging of hard to diagnose interrupt problems.
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If you don't know what to do here, say N.
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endmenu
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