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493cf04fd3
With the new API, tx descriptors can be written in one single pass instead of having to re-read and rewrite fields from multiple places. This makes the code easier to read and also slightly improves performance on embedded MIPS hardware. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
704 lines
19 KiB
C
704 lines
19 KiB
C
/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef ATH9K_H
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#define ATH9K_H
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#include <linux/etherdevice.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/leds.h>
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#include <linux/completion.h>
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#include "debug.h"
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#include "common.h"
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/*
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* Header for the ath9k.ko driver core *only* -- hw code nor any other driver
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* should rely on this file or its contents.
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*/
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struct ath_node;
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/* Macro to expand scalars to 64-bit objects */
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#define ito64(x) (sizeof(x) == 1) ? \
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(((unsigned long long int)(x)) & (0xff)) : \
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(sizeof(x) == 2) ? \
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(((unsigned long long int)(x)) & 0xffff) : \
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((sizeof(x) == 4) ? \
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(((unsigned long long int)(x)) & 0xffffffff) : \
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(unsigned long long int)(x))
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/* increment with wrap-around */
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#define INCR(_l, _sz) do { \
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(_l)++; \
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(_l) &= ((_sz) - 1); \
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} while (0)
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/* decrement with wrap-around */
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#define DECR(_l, _sz) do { \
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(_l)--; \
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(_l) &= ((_sz) - 1); \
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} while (0)
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#define TSF_TO_TU(_h,_l) \
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((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
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#define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
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struct ath_config {
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u16 txpowlimit;
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u8 cabqReadytime;
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};
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/*************************/
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/* Descriptor Management */
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/*************************/
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#define ATH_TXBUF_RESET(_bf) do { \
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(_bf)->bf_stale = false; \
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(_bf)->bf_lastbf = NULL; \
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(_bf)->bf_next = NULL; \
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memset(&((_bf)->bf_state), 0, \
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sizeof(struct ath_buf_state)); \
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} while (0)
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#define ATH_RXBUF_RESET(_bf) do { \
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(_bf)->bf_stale = false; \
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} while (0)
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/**
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* enum buffer_type - Buffer type flags
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*
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* @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
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* @BUF_AGGR: Indicates whether the buffer can be aggregated
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* (used in aggregation scheduling)
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*/
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enum buffer_type {
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BUF_AMPDU = BIT(0),
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BUF_AGGR = BIT(1),
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};
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#define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
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#define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
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#define ATH_TXSTATUS_RING_SIZE 64
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#define DS2PHYS(_dd, _ds) \
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((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
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#define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
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#define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
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struct ath_descdma {
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void *dd_desc;
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dma_addr_t dd_desc_paddr;
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u32 dd_desc_len;
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struct ath_buf *dd_bufptr;
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};
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int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
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struct list_head *head, const char *name,
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int nbuf, int ndesc, bool is_tx);
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void ath_descdma_cleanup(struct ath_softc *sc, struct ath_descdma *dd,
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struct list_head *head);
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/***********/
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/* RX / TX */
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/***********/
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#define ATH_RXBUF 512
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#define ATH_TXBUF 512
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#define ATH_TXBUF_RESERVE 5
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#define ATH_MAX_QDEPTH (ATH_TXBUF / 4 - ATH_TXBUF_RESERVE)
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#define ATH_TXMAXTRY 13
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#define TID_TO_WME_AC(_tid) \
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((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
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(((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
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(((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
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WME_AC_VO)
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#define ATH_AGGR_DELIM_SZ 4
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#define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
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/* number of delimiters for encryption padding */
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#define ATH_AGGR_ENCRYPTDELIM 10
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/* minimum h/w qdepth to be sustained to maximize aggregation */
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#define ATH_AGGR_MIN_QDEPTH 2
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#define ATH_AMPDU_SUBFRAME_DEFAULT 32
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#define IEEE80211_SEQ_SEQ_SHIFT 4
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#define IEEE80211_SEQ_MAX 4096
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#define IEEE80211_WEP_IVLEN 3
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#define IEEE80211_WEP_KIDLEN 1
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#define IEEE80211_WEP_CRCLEN 4
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#define IEEE80211_MAX_MPDU_LEN (3840 + FCS_LEN + \
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(IEEE80211_WEP_IVLEN + \
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IEEE80211_WEP_KIDLEN + \
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IEEE80211_WEP_CRCLEN))
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/* return whether a bit at index _n in bitmap _bm is set
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* _sz is the size of the bitmap */
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#define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
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((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
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/* return block-ack bitmap index given sequence and starting sequence */
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#define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
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/* returns delimiter padding required given the packet length */
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#define ATH_AGGR_GET_NDELIM(_len) \
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(((_len) >= ATH_AGGR_MINPLEN) ? 0 : \
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DIV_ROUND_UP(ATH_AGGR_MINPLEN - (_len), ATH_AGGR_DELIM_SZ))
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#define BAW_WITHIN(_start, _bawsz, _seqno) \
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((((_seqno) - (_start)) & 4095) < (_bawsz))
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#define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
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#define ATH_TX_COMPLETE_POLL_INT 1000
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enum ATH_AGGR_STATUS {
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ATH_AGGR_DONE,
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ATH_AGGR_BAW_CLOSED,
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ATH_AGGR_LIMITED,
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};
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#define ATH_TXFIFO_DEPTH 8
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struct ath_txq {
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int mac80211_qnum; /* mac80211 queue number, -1 means not mac80211 Q */
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u32 axq_qnum; /* ath9k hardware queue number */
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void *axq_link;
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struct list_head axq_q;
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spinlock_t axq_lock;
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u32 axq_depth;
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u32 axq_ampdu_depth;
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bool stopped;
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bool axq_tx_inprogress;
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struct list_head axq_acq;
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struct list_head txq_fifo[ATH_TXFIFO_DEPTH];
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u8 txq_headidx;
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u8 txq_tailidx;
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int pending_frames;
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};
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struct ath_atx_ac {
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struct ath_txq *txq;
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int sched;
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struct list_head list;
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struct list_head tid_q;
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bool clear_ps_filter;
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};
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struct ath_frame_info {
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struct ath_buf *bf;
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int framelen;
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enum ath9k_key_type keytype;
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u8 keyix;
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u8 retries;
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};
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struct ath_buf_state {
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u8 bf_type;
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u8 bfs_paprd;
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u8 ndelim;
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u16 seqno;
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unsigned long bfs_paprd_timestamp;
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};
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struct ath_buf {
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struct list_head list;
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struct ath_buf *bf_lastbf; /* last buf of this unit (a frame or
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an aggregate) */
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struct ath_buf *bf_next; /* next subframe in the aggregate */
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struct sk_buff *bf_mpdu; /* enclosing frame structure */
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void *bf_desc; /* virtual addr of desc */
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dma_addr_t bf_daddr; /* physical addr of desc */
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dma_addr_t bf_buf_addr; /* physical addr of data buffer, for DMA */
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bool bf_stale;
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struct ath_buf_state bf_state;
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};
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struct ath_atx_tid {
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struct list_head list;
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struct sk_buff_head buf_q;
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struct ath_node *an;
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struct ath_atx_ac *ac;
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unsigned long tx_buf[BITS_TO_LONGS(ATH_TID_MAX_BUFS)];
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u16 seq_start;
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u16 seq_next;
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u16 baw_size;
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int tidno;
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int baw_head; /* first un-acked tx buffer */
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int baw_tail; /* next unused tx buffer slot */
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int sched;
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int paused;
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u8 state;
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};
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struct ath_node {
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#ifdef CONFIG_ATH9K_DEBUGFS
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struct list_head list; /* for sc->nodes */
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struct ieee80211_sta *sta; /* station struct we're part of */
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#endif
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struct ath_atx_tid tid[WME_NUM_TID];
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struct ath_atx_ac ac[WME_NUM_AC];
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int ps_key;
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u16 maxampdu;
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u8 mpdudensity;
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bool sleeping;
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};
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#define AGGR_CLEANUP BIT(1)
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#define AGGR_ADDBA_COMPLETE BIT(2)
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#define AGGR_ADDBA_PROGRESS BIT(3)
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struct ath_tx_control {
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struct ath_txq *txq;
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struct ath_node *an;
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u8 paprd;
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};
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#define ATH_TX_ERROR 0x01
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#define ATH_TX_BAR 0x02
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/**
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* @txq_map: Index is mac80211 queue number. This is
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* not necessarily the same as the hardware queue number
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* (axq_qnum).
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*/
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struct ath_tx {
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u16 seq_no;
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u32 txqsetup;
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spinlock_t txbuflock;
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struct list_head txbuf;
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struct ath_txq txq[ATH9K_NUM_TX_QUEUES];
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struct ath_descdma txdma;
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struct ath_txq *txq_map[WME_NUM_AC];
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};
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struct ath_rx_edma {
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struct sk_buff_head rx_fifo;
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struct sk_buff_head rx_buffers;
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u32 rx_fifo_hwsize;
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};
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struct ath_rx {
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u8 defant;
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u8 rxotherant;
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u32 *rxlink;
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unsigned int rxfilter;
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spinlock_t rxbuflock;
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struct list_head rxbuf;
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struct ath_descdma rxdma;
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struct ath_buf *rx_bufptr;
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struct ath_rx_edma rx_edma[ATH9K_RX_QUEUE_MAX];
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struct sk_buff *frag;
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};
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int ath_startrecv(struct ath_softc *sc);
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bool ath_stoprecv(struct ath_softc *sc);
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void ath_flushrecv(struct ath_softc *sc);
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u32 ath_calcrxfilter(struct ath_softc *sc);
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int ath_rx_init(struct ath_softc *sc, int nbufs);
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void ath_rx_cleanup(struct ath_softc *sc);
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int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp);
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struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype);
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void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq);
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bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx);
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void ath_draintxq(struct ath_softc *sc,
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struct ath_txq *txq, bool retry_tx);
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void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an);
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void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
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void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq);
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int ath_tx_init(struct ath_softc *sc, int nbufs);
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void ath_tx_cleanup(struct ath_softc *sc);
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int ath_txq_update(struct ath_softc *sc, int qnum,
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struct ath9k_tx_queue_info *q);
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int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
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struct ath_tx_control *txctl);
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void ath_tx_tasklet(struct ath_softc *sc);
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void ath_tx_edma_tasklet(struct ath_softc *sc);
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int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
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u16 tid, u16 *ssn);
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void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
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void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
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void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
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bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an);
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/********/
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/* VIFs */
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/********/
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struct ath_vif {
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int av_bslot;
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bool is_bslot_active, primary_sta_vif;
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__le64 tsf_adjust; /* TSF adjustment for staggered beacons */
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struct ath_buf *av_bcbuf;
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};
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/*******************/
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/* Beacon Handling */
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/*******************/
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/*
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* Regardless of the number of beacons we stagger, (i.e. regardless of the
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* number of BSSIDs) if a given beacon does not go out even after waiting this
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* number of beacon intervals, the game's up.
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*/
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#define BSTUCK_THRESH 9
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#define ATH_BCBUF 4
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#define ATH_DEFAULT_BINTVAL 100 /* TU */
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#define ATH_DEFAULT_BMISS_LIMIT 10
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#define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
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struct ath_beacon_config {
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int beacon_interval;
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u16 listen_interval;
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u16 dtim_period;
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u16 bmiss_timeout;
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u8 dtim_count;
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};
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struct ath_beacon {
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enum {
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OK, /* no change needed */
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UPDATE, /* update pending */
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COMMIT /* beacon sent, commit change */
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} updateslot; /* slot time update fsm */
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u32 beaconq;
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u32 bmisscnt;
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u32 ast_be_xmit;
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u32 bc_tstamp;
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struct ieee80211_vif *bslot[ATH_BCBUF];
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int slottime;
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int slotupdate;
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struct ath9k_tx_queue_info beacon_qi;
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struct ath_descdma bdma;
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struct ath_txq *cabq;
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struct list_head bbuf;
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bool tx_processed;
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bool tx_last;
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};
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void ath_beacon_tasklet(unsigned long data);
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void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif);
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int ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_vif *vif);
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void ath_beacon_return(struct ath_softc *sc, struct ath_vif *avp);
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int ath_beaconq_config(struct ath_softc *sc);
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void ath_set_beacon(struct ath_softc *sc);
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void ath9k_set_beaconing_status(struct ath_softc *sc, bool status);
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/*******/
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/* ANI */
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/*******/
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#define ATH_STA_SHORT_CALINTERVAL 1000 /* 1 second */
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#define ATH_AP_SHORT_CALINTERVAL 100 /* 100 ms */
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#define ATH_ANI_POLLINTERVAL_OLD 100 /* 100 ms */
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#define ATH_ANI_POLLINTERVAL_NEW 1000 /* 1000 ms */
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#define ATH_LONG_CALINTERVAL_INT 1000 /* 1000 ms */
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#define ATH_LONG_CALINTERVAL 30000 /* 30 seconds */
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#define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes */
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#define ATH_PAPRD_TIMEOUT 100 /* msecs */
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void ath_reset_work(struct work_struct *work);
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void ath_hw_check(struct work_struct *work);
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void ath_hw_pll_work(struct work_struct *work);
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void ath_paprd_calibrate(struct work_struct *work);
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void ath_ani_calibrate(unsigned long data);
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void ath_start_ani(struct ath_common *common);
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/**********/
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/* BTCOEX */
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/**********/
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struct ath_btcoex {
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bool hw_timer_enabled;
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spinlock_t btcoex_lock;
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struct timer_list period_timer; /* Timer for BT period */
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u32 bt_priority_cnt;
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unsigned long bt_priority_time;
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int bt_stomp_type; /* Types of BT stomping */
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u32 btcoex_no_stomp; /* in usec */
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u32 btcoex_period; /* in usec */
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u32 btscan_no_stomp; /* in usec */
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struct ath_gen_timer *no_stomp_timer; /* Timer for no BT stomping */
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};
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int ath_init_btcoex_timer(struct ath_softc *sc);
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void ath9k_btcoex_timer_resume(struct ath_softc *sc);
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void ath9k_btcoex_timer_pause(struct ath_softc *sc);
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/********************/
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/* LED Control */
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/********************/
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#define ATH_LED_PIN_DEF 1
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#define ATH_LED_PIN_9287 8
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#define ATH_LED_PIN_9300 10
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#define ATH_LED_PIN_9485 6
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#define ATH_LED_PIN_9480 0
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#ifdef CONFIG_MAC80211_LEDS
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void ath_init_leds(struct ath_softc *sc);
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void ath_deinit_leds(struct ath_softc *sc);
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#else
|
|
static inline void ath_init_leds(struct ath_softc *sc)
|
|
{
|
|
}
|
|
|
|
static inline void ath_deinit_leds(struct ath_softc *sc)
|
|
{
|
|
}
|
|
#endif
|
|
|
|
|
|
/* Antenna diversity/combining */
|
|
#define ATH_ANT_RX_CURRENT_SHIFT 4
|
|
#define ATH_ANT_RX_MAIN_SHIFT 2
|
|
#define ATH_ANT_RX_MASK 0x3
|
|
|
|
#define ATH_ANT_DIV_COMB_SHORT_SCAN_INTR 50
|
|
#define ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT 0x100
|
|
#define ATH_ANT_DIV_COMB_MAX_PKTCOUNT 0x200
|
|
#define ATH_ANT_DIV_COMB_INIT_COUNT 95
|
|
#define ATH_ANT_DIV_COMB_MAX_COUNT 100
|
|
#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO 30
|
|
#define ATH_ANT_DIV_COMB_ALT_ANT_RATIO2 20
|
|
|
|
#define ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA -1
|
|
#define ATH_ANT_DIV_COMB_LNA1_DELTA_HI -4
|
|
#define ATH_ANT_DIV_COMB_LNA1_DELTA_MID -2
|
|
#define ATH_ANT_DIV_COMB_LNA1_DELTA_LOW 2
|
|
|
|
enum ath9k_ant_div_comb_lna_conf {
|
|
ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2,
|
|
ATH_ANT_DIV_COMB_LNA2,
|
|
ATH_ANT_DIV_COMB_LNA1,
|
|
ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2,
|
|
};
|
|
|
|
struct ath_ant_comb {
|
|
u16 count;
|
|
u16 total_pkt_count;
|
|
bool scan;
|
|
bool scan_not_start;
|
|
int main_total_rssi;
|
|
int alt_total_rssi;
|
|
int alt_recv_cnt;
|
|
int main_recv_cnt;
|
|
int rssi_lna1;
|
|
int rssi_lna2;
|
|
int rssi_add;
|
|
int rssi_sub;
|
|
int rssi_first;
|
|
int rssi_second;
|
|
int rssi_third;
|
|
bool alt_good;
|
|
int quick_scan_cnt;
|
|
int main_conf;
|
|
enum ath9k_ant_div_comb_lna_conf first_quick_scan_conf;
|
|
enum ath9k_ant_div_comb_lna_conf second_quick_scan_conf;
|
|
int first_bias;
|
|
int second_bias;
|
|
bool first_ratio;
|
|
bool second_ratio;
|
|
unsigned long scan_start_time;
|
|
};
|
|
|
|
/********************/
|
|
/* Main driver core */
|
|
/********************/
|
|
|
|
/*
|
|
* Default cache line size, in bytes.
|
|
* Used when PCI device not fully initialized by bootrom/BIOS
|
|
*/
|
|
#define DEFAULT_CACHELINE 32
|
|
#define ATH_REGCLASSIDS_MAX 10
|
|
#define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
|
|
#define ATH_MAX_SW_RETRIES 10
|
|
#define ATH_CHAN_MAX 255
|
|
|
|
#define ATH_TXPOWER_MAX 100 /* .5 dBm units */
|
|
#define ATH_RATE_DUMMY_MARKER 0
|
|
|
|
#define SC_OP_INVALID BIT(0)
|
|
#define SC_OP_BEACONS BIT(1)
|
|
#define SC_OP_RXAGGR BIT(2)
|
|
#define SC_OP_TXAGGR BIT(3)
|
|
#define SC_OP_OFFCHANNEL BIT(4)
|
|
#define SC_OP_PREAMBLE_SHORT BIT(5)
|
|
#define SC_OP_PROTECT_ENABLE BIT(6)
|
|
#define SC_OP_RXFLUSH BIT(7)
|
|
#define SC_OP_LED_ASSOCIATED BIT(8)
|
|
#define SC_OP_LED_ON BIT(9)
|
|
#define SC_OP_TSF_RESET BIT(11)
|
|
#define SC_OP_BT_PRIORITY_DETECTED BIT(12)
|
|
#define SC_OP_BT_SCAN BIT(13)
|
|
#define SC_OP_ANI_RUN BIT(14)
|
|
#define SC_OP_PRIM_STA_VIF BIT(15)
|
|
|
|
/* Powersave flags */
|
|
#define PS_WAIT_FOR_BEACON BIT(0)
|
|
#define PS_WAIT_FOR_CAB BIT(1)
|
|
#define PS_WAIT_FOR_PSPOLL_DATA BIT(2)
|
|
#define PS_WAIT_FOR_TX_ACK BIT(3)
|
|
#define PS_BEACON_SYNC BIT(4)
|
|
|
|
struct ath_rate_table;
|
|
|
|
struct ath9k_vif_iter_data {
|
|
const u8 *hw_macaddr; /* phy's hardware address, set
|
|
* before starting iteration for
|
|
* valid bssid mask.
|
|
*/
|
|
u8 mask[ETH_ALEN]; /* bssid mask */
|
|
int naps; /* number of AP vifs */
|
|
int nmeshes; /* number of mesh vifs */
|
|
int nstations; /* number of station vifs */
|
|
int nwds; /* number of WDS vifs */
|
|
int nadhocs; /* number of adhoc vifs */
|
|
int nothers; /* number of vifs not specified above. */
|
|
};
|
|
|
|
struct ath_softc {
|
|
struct ieee80211_hw *hw;
|
|
struct device *dev;
|
|
|
|
int chan_idx;
|
|
int chan_is_ht;
|
|
struct survey_info *cur_survey;
|
|
struct survey_info survey[ATH9K_NUM_CHANNELS];
|
|
|
|
struct tasklet_struct intr_tq;
|
|
struct tasklet_struct bcon_tasklet;
|
|
struct ath_hw *sc_ah;
|
|
void __iomem *mem;
|
|
int irq;
|
|
spinlock_t sc_serial_rw;
|
|
spinlock_t sc_pm_lock;
|
|
spinlock_t sc_pcu_lock;
|
|
struct mutex mutex;
|
|
struct work_struct paprd_work;
|
|
struct work_struct hw_check_work;
|
|
struct work_struct hw_reset_work;
|
|
struct completion paprd_complete;
|
|
|
|
unsigned int hw_busy_count;
|
|
|
|
u32 intrstatus;
|
|
u32 sc_flags; /* SC_OP_* */
|
|
u16 ps_flags; /* PS_* */
|
|
u16 curtxpow;
|
|
bool ps_enabled;
|
|
bool ps_idle;
|
|
short nbcnvifs;
|
|
short nvifs;
|
|
unsigned long ps_usecount;
|
|
|
|
struct ath_config config;
|
|
struct ath_rx rx;
|
|
struct ath_tx tx;
|
|
struct ath_beacon beacon;
|
|
struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
|
|
|
|
#ifdef CONFIG_MAC80211_LEDS
|
|
bool led_registered;
|
|
char led_name[32];
|
|
struct led_classdev led_cdev;
|
|
#endif
|
|
|
|
struct ath9k_hw_cal_data caldata;
|
|
int last_rssi;
|
|
|
|
#ifdef CONFIG_ATH9K_DEBUGFS
|
|
struct ath9k_debug debug;
|
|
spinlock_t nodes_lock;
|
|
struct list_head nodes; /* basically, stations */
|
|
unsigned int tx_complete_poll_work_seen;
|
|
#endif
|
|
struct ath_beacon_config cur_beacon_conf;
|
|
struct delayed_work tx_complete_work;
|
|
struct delayed_work hw_pll_work;
|
|
struct ath_btcoex btcoex;
|
|
|
|
struct ath_descdma txsdma;
|
|
|
|
struct ath_ant_comb ant_comb;
|
|
u8 ant_tx, ant_rx;
|
|
};
|
|
|
|
void ath9k_tasklet(unsigned long data);
|
|
int ath_cabq_update(struct ath_softc *);
|
|
|
|
static inline void ath_read_cachesize(struct ath_common *common, int *csz)
|
|
{
|
|
common->bus_ops->read_cachesize(common, csz);
|
|
}
|
|
|
|
extern struct ieee80211_ops ath9k_ops;
|
|
extern int ath9k_modparam_nohwcrypt;
|
|
extern int led_blink;
|
|
extern bool is_ath9k_unloaded;
|
|
|
|
irqreturn_t ath_isr(int irq, void *dev);
|
|
int ath9k_init_device(u16 devid, struct ath_softc *sc,
|
|
const struct ath_bus_ops *bus_ops);
|
|
void ath9k_deinit_device(struct ath_softc *sc);
|
|
void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw);
|
|
void ath9k_reload_chainmask_settings(struct ath_softc *sc);
|
|
|
|
void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw);
|
|
bool ath9k_uses_beacons(int type);
|
|
|
|
#ifdef CONFIG_ATH9K_PCI
|
|
int ath_pci_init(void);
|
|
void ath_pci_exit(void);
|
|
#else
|
|
static inline int ath_pci_init(void) { return 0; };
|
|
static inline void ath_pci_exit(void) {};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ATH9K_AHB
|
|
int ath_ahb_init(void);
|
|
void ath_ahb_exit(void);
|
|
#else
|
|
static inline int ath_ahb_init(void) { return 0; };
|
|
static inline void ath_ahb_exit(void) {};
|
|
#endif
|
|
|
|
void ath9k_ps_wakeup(struct ath_softc *sc);
|
|
void ath9k_ps_restore(struct ath_softc *sc);
|
|
|
|
u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate);
|
|
|
|
void ath_start_rfkill_poll(struct ath_softc *sc);
|
|
extern void ath9k_rfkill_poll_state(struct ieee80211_hw *hw);
|
|
void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
|
|
struct ieee80211_vif *vif,
|
|
struct ath9k_vif_iter_data *iter_data);
|
|
|
|
|
|
#endif /* ATH9K_H */
|