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8def929c40
Add support for the modem clock controller found on SC7180 based devices. This would allow modem drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Link: https://lkml.kernel.org/r/1584596131-22741-4-git-send-email-tdas@codeaurora.org Tested-by: Sibi Sankar <sibis@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
144 lines
3.1 KiB
C
144 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/pm_clock.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,mss-sc7180.h>
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#include "clk-regmap.h"
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#include "clk-branch.h"
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#include "common.h"
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static struct clk_branch mss_axi_nav_clk = {
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.halt_reg = 0x20bc,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x20bc,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "mss_axi_nav_clk",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "gcc_mss_nav_axi",
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch mss_axi_crypto_clk = {
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.halt_reg = 0x20cc,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x20cc,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "mss_axi_crypto_clk",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "gcc_mss_mfab_axis",
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},
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.num_parents = 1,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static const struct regmap_config mss_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.fast_io = true,
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.max_register = 0x41aa0cc,
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};
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static struct clk_regmap *mss_sc7180_clocks[] = {
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[MSS_AXI_CRYPTO_CLK] = &mss_axi_crypto_clk.clkr,
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[MSS_AXI_NAV_CLK] = &mss_axi_nav_clk.clkr,
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};
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static const struct qcom_cc_desc mss_sc7180_desc = {
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.config = &mss_regmap_config,
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.clks = mss_sc7180_clocks,
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.num_clks = ARRAY_SIZE(mss_sc7180_clocks),
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};
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static int mss_sc7180_probe(struct platform_device *pdev)
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{
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int ret;
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pm_runtime_enable(&pdev->dev);
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ret = pm_clk_create(&pdev->dev);
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if (ret)
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goto disable_pm_runtime;
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ret = pm_clk_add(&pdev->dev, "cfg_ahb");
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if (ret < 0) {
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dev_err(&pdev->dev, "failed to acquire iface clock\n");
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goto destroy_pm_clk;
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}
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ret = qcom_cc_probe(pdev, &mss_sc7180_desc);
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if (ret < 0)
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goto destroy_pm_clk;
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return 0;
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destroy_pm_clk:
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pm_clk_destroy(&pdev->dev);
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disable_pm_runtime:
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pm_runtime_disable(&pdev->dev);
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return ret;
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}
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static int mss_sc7180_remove(struct platform_device *pdev)
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{
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pm_clk_destroy(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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return 0;
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}
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static const struct dev_pm_ops mss_sc7180_pm_ops = {
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SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
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};
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static const struct of_device_id mss_sc7180_match_table[] = {
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{ .compatible = "qcom,sc7180-mss" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, mss_sc7180_match_table);
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static struct platform_driver mss_sc7180_driver = {
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.probe = mss_sc7180_probe,
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.remove = mss_sc7180_remove,
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.driver = {
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.name = "sc7180-mss",
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.of_match_table = mss_sc7180_match_table,
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.pm = &mss_sc7180_pm_ops,
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},
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};
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static int __init mss_sc7180_init(void)
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{
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return platform_driver_register(&mss_sc7180_driver);
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}
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subsys_initcall(mss_sc7180_init);
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static void __exit mss_sc7180_exit(void)
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{
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platform_driver_unregister(&mss_sc7180_driver);
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}
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module_exit(mss_sc7180_exit);
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MODULE_DESCRIPTION("QTI MSS SC7180 Driver");
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MODULE_LICENSE("GPL v2");
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