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Update to commit 9c9b415c50 [MIPS:
Reimplement get_cycles().]
On systems were for whatever reasons we can't use the cycle counter, fall
back to the c0_random register as an entropy source. It has however a
very small range that makes it suitable for random_get_entropy only and
not get_cycles.
This optimised version compiles to 8 instructions in the fast path even in
the worst case of all the conditions to check being variable (including a
MFC0 move delay slot that is only required for very old processors):
828: 8cf90000 lw t9,0(a3)
828: R_MIPS_LO16 jiffies
82c: 40057800 mfc0 a1,c0_prid
830: 3c0200ff lui v0,0xff
834: 00a21024 and v0,a1,v0
838: 1040007d beqz v0,a30 <add_interrupt_randomness+0x22c>
83c: 3c030000 lui v1,0x0
83c: R_MIPS_HI16 cpu_data
840: 40024800 mfc0 v0,c0_count
844: 00000000 nop
848: 00409021 move s2,v0
84c: 8ce20000 lw v0,0(a3)
84c: R_MIPS_LO16 jiffies
On most targets the sequence will be shorter and on some it will reduce to
a single `MFC0 <reg>,c0_count', as all MIPS architecture (i.e. non-legacy
MIPS) processors require the CP0 Count register to be present.
The only known exception that reports MIPS architecture compliance, but
contrary to that lacks CP0 Count is the Ingenic JZ4740 thingy. For broken
platforms like that this code requires cpu_has_counter to be hardcoded to
0 (i.e. no variable setting is permitted) so as not to penalise all the
other good platforms out there.
The asm barrier is required so that the compiler does not pull any
potentially costly (cold cache!) `cpu_data' variable access into the fast
path.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Theodore Ts'o <tytso@mit.edu>
Cc: John Crispin <blogic@openwrt.org>
Cc: Andrew McGregor <andrewmcgr@gmail.com>
Cc: Dave Taht <dave.taht@bufferbloat.net>
Cc: Felix Fietkau <nbd@nbd.name>
Cc: Simon Kelley <simon@thekelleys.org.uk>
Cc: Jim Gettys <jg@freedesktop.org>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6702/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
104 lines
3.0 KiB
C
104 lines
3.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1998, 1999, 2003 by Ralf Baechle
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* Copyright (C) 2014 by Maciej W. Rozycki
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*/
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#ifndef _ASM_TIMEX_H
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#define _ASM_TIMEX_H
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#include <asm/cpu.h>
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#include <asm/cpu-features.h>
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#include <asm/mipsregs.h>
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#include <asm/cpu-type.h>
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/*
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* This is the clock rate of the i8253 PIT. A MIPS system may not have
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* a PIT by the symbol is used all over the kernel including some APIs.
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* So keeping it defined to the number for the PIT is the only sane thing
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* for now.
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*/
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#define CLOCK_TICK_RATE 1193182
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/*
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* Standard way to access the cycle counter.
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* Currently only used on SMP for scheduling.
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*
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* Only the low 32 bits are available as a continuously counting entity.
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* But this only means we'll force a reschedule every 8 seconds or so,
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* which isn't an evil thing.
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*
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* We know that all SMP capable CPUs have cycle counters.
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*/
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typedef unsigned int cycles_t;
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/*
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* On R4000/R4400 before version 5.0 an erratum exists such that if the
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* cycle counter is read in the exact moment that it is matching the
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* compare register, no interrupt will be generated.
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*
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* There is a suggested workaround and also the erratum can't strike if
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* the compare interrupt isn't being used as the clock source device.
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* However for now the implementaton of this function doesn't get these
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* fine details right.
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*/
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static inline int can_use_mips_counter(unsigned int prid)
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{
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int comp = (prid & PRID_COMP_MASK) != PRID_COMP_LEGACY;
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if (__builtin_constant_p(cpu_has_counter) && !cpu_has_counter)
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return 0;
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else if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r)
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return 1;
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else if (likely(!__builtin_constant_p(cpu_has_mips_r) && comp))
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return 1;
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/* Make sure we don't peek at cpu_data[0].options in the fast path! */
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if (!__builtin_constant_p(cpu_has_counter))
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asm volatile("" : "=m" (cpu_data[0].options));
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if (likely(cpu_has_counter &&
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prid >= (PRID_IMP_R4000 | PRID_REV_ENCODE_44(5, 0))))
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return 1;
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else
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return 0;
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}
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static inline cycles_t get_cycles(void)
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{
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if (can_use_mips_counter(read_c0_prid()))
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return read_c0_count();
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else
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return 0; /* no usable counter */
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}
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/*
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* Like get_cycles - but where c0_count is not available we desperately
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* use c0_random in an attempt to get at least a little bit of entropy.
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*
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* R6000 and R6000A neither have a count register nor a random register.
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* That leaves no entropy source in the CPU itself.
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*/
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static inline unsigned long random_get_entropy(void)
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{
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unsigned int prid = read_c0_prid();
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unsigned int imp = prid & PRID_IMP_MASK;
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if (can_use_mips_counter(prid))
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return read_c0_count();
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else if (likely(imp != PRID_IMP_R6000 && imp != PRID_IMP_R6000A))
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return read_c0_random();
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else
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return 0; /* no usable register */
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}
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#define random_get_entropy random_get_entropy
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#endif /* __KERNEL__ */
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#endif /* _ASM_TIMEX_H */
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