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MSIOF Base Address H'E6xx can be accessed by CPU and DMAC. MSIOF Base Address H'E7xx for DMAC was removed from H/W manual. Signed-off-by: Ryo Kataoka <ryo.kataoka.wt@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
72 lines
2.6 KiB
Plaintext
72 lines
2.6 KiB
Plaintext
Renesas MSIOF spi controller
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Required properties:
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- compatible : "renesas,msiof-<soctype>" for SoCs,
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"renesas,sh-msiof" for SuperH, or
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"renesas,sh-mobile-msiof" for SH Mobile series.
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Examples with soctypes are:
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"renesas,msiof-r8a7790" (R-Car H2)
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"renesas,msiof-r8a7791" (R-Car M2-W)
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"renesas,msiof-r8a7792" (R-Car V2H)
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"renesas,msiof-r8a7793" (R-Car M2-N)
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"renesas,msiof-r8a7794" (R-Car E2)
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- reg : A list of offsets and lengths of the register sets for
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the device.
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If only one register set is present, it is to be used
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by both the CPU and the DMA engine.
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If two register sets are present, the first is to be
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used by the CPU, and the second is to be used by the
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DMA engine.
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- interrupt-parent : The phandle for the interrupt controller that
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services interrupts for this device
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- interrupts : Interrupt specifier
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- #address-cells : Must be <1>
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- #size-cells : Must be <0>
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Optional properties:
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- clocks : Must contain a reference to the functional clock.
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- num-cs : Total number of chip-selects (default is 1)
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- dmas : Must contain a list of two references to DMA
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specifiers, one for transmission, and one for
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reception.
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- dma-names : Must contain a list of two DMA names, "tx" and "rx".
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- renesas,dtdl : delay sync signal (setup) in transmit mode.
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Must contain one of the following values:
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0 (no bit delay)
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50 (0.5-clock-cycle delay)
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100 (1-clock-cycle delay)
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150 (1.5-clock-cycle delay)
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200 (2-clock-cycle delay)
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- renesas,syncdl : delay sync signal (hold) in transmit mode.
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Must contain one of the following values:
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0 (no bit delay)
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50 (0.5-clock-cycle delay)
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100 (1-clock-cycle delay)
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150 (1.5-clock-cycle delay)
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200 (2-clock-cycle delay)
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300 (3-clock-cycle delay)
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Optional properties, deprecated for soctype-specific bindings:
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- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
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(default is 64)
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- renesas,rx-fifo-size : Overrides the default rx fifo size given in words
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(default is 64, or 256 on R-Car Gen2)
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Pinctrl properties might be needed, too. See
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Documentation/devicetree/bindings/pinctrl/renesas,*.
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Example:
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msiof0: spi@e6e20000 {
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compatible = "renesas,msiof-r8a7791";
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reg = <0 0xe6e20000 0 0x0064>;
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interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
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dmas = <&dmac0 0x51>, <&dmac0 0x52>;
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dma-names = "tx", "rx";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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