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e7a877b2fa
devm_of_phy_get_by_index() can fail for a number of reasons besides probe deferral. It can for example return -ENOMEM if it runs out of memory as it tries to allocate devres structures. Propagating only -EPROBE_DEFER is problematic because it results in these legitimately fatal errors being treated as "PHY not specified in DT". What we really want is to ignore the optional PHYs only if they have not been specified in DT. devm_of_phy_get_by_index() returns -ENODEV in this case, so that's the special case that we need to handle. So we propagate all errors, except -ENODEV, so that real failures will still cause the driver to fail probe. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Andrew Murray <andrew.murray@arm.com> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
361 lines
9.0 KiB
C
361 lines
9.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Marvell Armada-8K SoCs
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*
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* Armada-8K PCIe Glue Layer Source Code
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*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Author: Yehuda Yitshak <yehuday@marvell.com>
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* Author: Shadi Ammouri <shadi@marvell.com>
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/pci.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/of_pci.h>
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#include <linux/of_irq.h>
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#include "pcie-designware.h"
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#define ARMADA8K_PCIE_MAX_LANES PCIE_LNK_X4
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struct armada8k_pcie {
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struct dw_pcie *pci;
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struct clk *clk;
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struct clk *clk_reg;
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struct phy *phy[ARMADA8K_PCIE_MAX_LANES];
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unsigned int phy_count;
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};
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#define PCIE_VENDOR_REGS_OFFSET 0x8000
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#define PCIE_GLOBAL_CONTROL_REG (PCIE_VENDOR_REGS_OFFSET + 0x0)
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#define PCIE_APP_LTSSM_EN BIT(2)
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#define PCIE_DEVICE_TYPE_SHIFT 4
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#define PCIE_DEVICE_TYPE_MASK 0xF
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#define PCIE_DEVICE_TYPE_RC 0x4 /* Root complex */
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#define PCIE_GLOBAL_STATUS_REG (PCIE_VENDOR_REGS_OFFSET + 0x8)
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#define PCIE_GLB_STS_RDLH_LINK_UP BIT(1)
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#define PCIE_GLB_STS_PHY_LINK_UP BIT(9)
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#define PCIE_GLOBAL_INT_CAUSE1_REG (PCIE_VENDOR_REGS_OFFSET + 0x1C)
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#define PCIE_GLOBAL_INT_MASK1_REG (PCIE_VENDOR_REGS_OFFSET + 0x20)
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#define PCIE_INT_A_ASSERT_MASK BIT(9)
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#define PCIE_INT_B_ASSERT_MASK BIT(10)
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#define PCIE_INT_C_ASSERT_MASK BIT(11)
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#define PCIE_INT_D_ASSERT_MASK BIT(12)
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#define PCIE_ARCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x50)
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#define PCIE_AWCACHE_TRC_REG (PCIE_VENDOR_REGS_OFFSET + 0x54)
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#define PCIE_ARUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x5C)
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#define PCIE_AWUSER_REG (PCIE_VENDOR_REGS_OFFSET + 0x60)
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/*
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* AR/AW Cache defaults: Normal memory, Write-Back, Read / Write
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* allocate
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*/
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#define ARCACHE_DEFAULT_VALUE 0x3511
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#define AWCACHE_DEFAULT_VALUE 0x5311
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#define DOMAIN_OUTER_SHAREABLE 0x2
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#define AX_USER_DOMAIN_MASK 0x3
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#define AX_USER_DOMAIN_SHIFT 4
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#define to_armada8k_pcie(x) dev_get_drvdata((x)->dev)
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static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie)
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{
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int i;
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for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) {
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phy_power_off(pcie->phy[i]);
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phy_exit(pcie->phy[i]);
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}
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}
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static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie)
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{
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int ret;
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int i;
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for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) {
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ret = phy_init(pcie->phy[i]);
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if (ret)
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return ret;
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ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE,
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pcie->phy_count);
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if (ret) {
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phy_exit(pcie->phy[i]);
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return ret;
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}
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ret = phy_power_on(pcie->phy[i]);
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if (ret) {
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phy_exit(pcie->phy[i]);
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return ret;
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}
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}
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return 0;
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}
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static int armada8k_pcie_setup_phys(struct armada8k_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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struct device_node *node = dev->of_node;
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int ret = 0;
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int i;
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for (i = 0; i < ARMADA8K_PCIE_MAX_LANES; i++) {
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pcie->phy[i] = devm_of_phy_get_by_index(dev, node, i);
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if (IS_ERR(pcie->phy[i])) {
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if (PTR_ERR(pcie->phy[i]) != -ENODEV)
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return PTR_ERR(pcie->phy[i]);
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pcie->phy[i] = NULL;
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continue;
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}
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pcie->phy_count++;
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}
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/* Old bindings miss the PHY handle, so just warn if there is no PHY */
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if (!pcie->phy_count)
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dev_warn(dev, "No available PHY\n");
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ret = armada8k_pcie_enable_phys(pcie);
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if (ret)
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dev_err(dev, "Failed to initialize PHY(s) (%d)\n", ret);
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return ret;
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}
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static int armada8k_pcie_link_up(struct dw_pcie *pci)
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{
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u32 reg;
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u32 mask = PCIE_GLB_STS_RDLH_LINK_UP | PCIE_GLB_STS_PHY_LINK_UP;
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reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_STATUS_REG);
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if ((reg & mask) == mask)
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return 1;
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dev_dbg(pci->dev, "No link detected (Global-Status: 0x%08x).\n", reg);
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return 0;
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}
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static void armada8k_pcie_establish_link(struct armada8k_pcie *pcie)
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{
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struct dw_pcie *pci = pcie->pci;
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u32 reg;
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if (!dw_pcie_link_up(pci)) {
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/* Disable LTSSM state machine to enable configuration */
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reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
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reg &= ~(PCIE_APP_LTSSM_EN);
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dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
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}
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/* Set the device to root complex mode */
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reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
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reg &= ~(PCIE_DEVICE_TYPE_MASK << PCIE_DEVICE_TYPE_SHIFT);
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reg |= PCIE_DEVICE_TYPE_RC << PCIE_DEVICE_TYPE_SHIFT;
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dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
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/* Set the PCIe master AxCache attributes */
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dw_pcie_writel_dbi(pci, PCIE_ARCACHE_TRC_REG, ARCACHE_DEFAULT_VALUE);
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dw_pcie_writel_dbi(pci, PCIE_AWCACHE_TRC_REG, AWCACHE_DEFAULT_VALUE);
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/* Set the PCIe master AxDomain attributes */
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reg = dw_pcie_readl_dbi(pci, PCIE_ARUSER_REG);
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reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
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reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
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dw_pcie_writel_dbi(pci, PCIE_ARUSER_REG, reg);
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reg = dw_pcie_readl_dbi(pci, PCIE_AWUSER_REG);
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reg &= ~(AX_USER_DOMAIN_MASK << AX_USER_DOMAIN_SHIFT);
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reg |= DOMAIN_OUTER_SHAREABLE << AX_USER_DOMAIN_SHIFT;
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dw_pcie_writel_dbi(pci, PCIE_AWUSER_REG, reg);
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/* Enable INT A-D interrupts */
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reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG);
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reg |= PCIE_INT_A_ASSERT_MASK | PCIE_INT_B_ASSERT_MASK |
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PCIE_INT_C_ASSERT_MASK | PCIE_INT_D_ASSERT_MASK;
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dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_MASK1_REG, reg);
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if (!dw_pcie_link_up(pci)) {
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/* Configuration done. Start LTSSM */
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reg = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_CONTROL_REG);
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reg |= PCIE_APP_LTSSM_EN;
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dw_pcie_writel_dbi(pci, PCIE_GLOBAL_CONTROL_REG, reg);
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}
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/* Wait until the link becomes active again */
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if (dw_pcie_wait_for_link(pci))
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dev_err(pci->dev, "Link not up after reconfiguration\n");
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}
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static int armada8k_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct armada8k_pcie *pcie = to_armada8k_pcie(pci);
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dw_pcie_setup_rc(pp);
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armada8k_pcie_establish_link(pcie);
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return 0;
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}
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static irqreturn_t armada8k_pcie_irq_handler(int irq, void *arg)
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{
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struct armada8k_pcie *pcie = arg;
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struct dw_pcie *pci = pcie->pci;
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u32 val;
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/*
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* Interrupts are directly handled by the device driver of the
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* PCI device. However, they are also latched into the PCIe
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* controller, so we simply discard them.
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*/
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val = dw_pcie_readl_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG);
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dw_pcie_writel_dbi(pci, PCIE_GLOBAL_INT_CAUSE1_REG, val);
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return IRQ_HANDLED;
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}
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static const struct dw_pcie_host_ops armada8k_pcie_host_ops = {
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.host_init = armada8k_pcie_host_init,
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};
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static int armada8k_add_pcie_port(struct armada8k_pcie *pcie,
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struct platform_device *pdev)
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{
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struct dw_pcie *pci = pcie->pci;
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struct pcie_port *pp = &pci->pp;
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struct device *dev = &pdev->dev;
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int ret;
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pp->ops = &armada8k_pcie_host_ops;
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pp->irq = platform_get_irq(pdev, 0);
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if (pp->irq < 0) {
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dev_err(dev, "failed to get irq for port\n");
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return pp->irq;
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}
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ret = devm_request_irq(dev, pp->irq, armada8k_pcie_irq_handler,
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IRQF_SHARED, "armada8k-pcie", pcie);
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if (ret) {
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dev_err(dev, "failed to request irq %d\n", pp->irq);
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return ret;
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}
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "failed to initialize host: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.link_up = armada8k_pcie_link_up,
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};
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static int armada8k_pcie_probe(struct platform_device *pdev)
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{
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struct dw_pcie *pci;
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struct armada8k_pcie *pcie;
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struct device *dev = &pdev->dev;
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struct resource *base;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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pcie->pci = pci;
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pcie->clk = devm_clk_get(dev, NULL);
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if (IS_ERR(pcie->clk))
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return PTR_ERR(pcie->clk);
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ret = clk_prepare_enable(pcie->clk);
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if (ret)
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return ret;
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pcie->clk_reg = devm_clk_get(dev, "reg");
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if (pcie->clk_reg == ERR_PTR(-EPROBE_DEFER)) {
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ret = -EPROBE_DEFER;
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goto fail;
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}
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if (!IS_ERR(pcie->clk_reg)) {
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ret = clk_prepare_enable(pcie->clk_reg);
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if (ret)
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goto fail_clkreg;
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}
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/* Get the dw-pcie unit configuration/control registers base. */
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base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
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pci->dbi_base = devm_pci_remap_cfg_resource(dev, base);
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if (IS_ERR(pci->dbi_base)) {
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dev_err(dev, "couldn't remap regs base %p\n", base);
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ret = PTR_ERR(pci->dbi_base);
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goto fail_clkreg;
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}
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ret = armada8k_pcie_setup_phys(pcie);
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if (ret)
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goto fail_clkreg;
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platform_set_drvdata(pdev, pcie);
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ret = armada8k_add_pcie_port(pcie, pdev);
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if (ret)
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goto disable_phy;
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return 0;
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disable_phy:
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armada8k_pcie_disable_phys(pcie);
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fail_clkreg:
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clk_disable_unprepare(pcie->clk_reg);
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fail:
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clk_disable_unprepare(pcie->clk);
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return ret;
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}
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static const struct of_device_id armada8k_pcie_of_match[] = {
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{ .compatible = "marvell,armada8k-pcie", },
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{},
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};
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static struct platform_driver armada8k_pcie_driver = {
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.probe = armada8k_pcie_probe,
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.driver = {
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.name = "armada8k-pcie",
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.of_match_table = of_match_ptr(armada8k_pcie_of_match),
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(armada8k_pcie_driver);
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