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1602df02f3
CTR_EL0.IDC reports the data cache clean requirements for instruction
to data coherence. However, if the field is 0, we need to check the
CLIDR_EL1 fields to detect the status of the feature. Currently we
don't do this and generate a warning with tainting the kernel, when
there is a mismatch in the field among the CPUs. Also the userspace
doesn't have a reliable way to check the CLIDR_EL1 register to check
the status.
This patch fixes the problem by checking the CLIDR_EL1 fields, when
(CTR_EL0.IDC == 0) and updates the kernel's copy of the CTR_EL0 for
the CPU with the actual status of the feature. This would allow the
sanity check infrastructure to do the proper checking of the fields
and also allow the CTR_EL0 emulation code to supply the real status
of the feature.
Now, if a CPU has raw CTR_EL0.IDC == 0 and effective IDC == 1 (with
overall system wide IDC == 1), we need to expose the real value to
the user. So, we trap CTR_EL0 access on the CPU which reports incorrect
CTR_EL0.IDC.
Fixes: commit 6ae4b6e057 ("arm64: Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC")
Cc: Shanker Donthineni <shankerd@codeaurora.org>
Cc: Philip Elcan <pelcan@codeaurora.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_CACHE_H
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#define __ASM_CACHE_H
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#include <asm/cputype.h>
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#define CTR_L1IP_SHIFT 14
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#define CTR_L1IP_MASK 3
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#define CTR_DMINLINE_SHIFT 16
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#define CTR_IMINLINE_SHIFT 0
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#define CTR_ERG_SHIFT 20
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#define CTR_CWG_SHIFT 24
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#define CTR_CWG_MASK 15
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#define CTR_IDC_SHIFT 28
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#define CTR_DIC_SHIFT 29
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#define CTR_CACHE_MINLINE_MASK \
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(0xf << CTR_DMINLINE_SHIFT | 0xf << CTR_IMINLINE_SHIFT)
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#define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK)
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#define ICACHE_POLICY_VPIPT 0
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#define ICACHE_POLICY_VIPT 2
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#define ICACHE_POLICY_PIPT 3
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#define L1_CACHE_SHIFT (6)
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define CLIDR_LOUU_SHIFT 27
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#define CLIDR_LOC_SHIFT 24
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#define CLIDR_LOUIS_SHIFT 21
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#define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
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#define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
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#define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
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/*
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* Memory returned by kmalloc() may be used for DMA, so we must make
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* sure that all such allocations are cache aligned. Otherwise,
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* unrelated code may cause parts of the buffer to be read into the
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* cache before the transfer is done, causing old data to be seen by
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* the CPU.
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*/
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#define ARCH_DMA_MINALIGN (128)
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#define ICACHEF_ALIASING 0
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#define ICACHEF_VPIPT 1
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extern unsigned long __icache_flags;
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/*
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* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
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* permitted in the I-cache.
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*/
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static inline int icache_is_aliasing(void)
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{
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return test_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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static inline int icache_is_vpipt(void)
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{
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return test_bit(ICACHEF_VPIPT, &__icache_flags);
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}
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static inline u32 cache_type_cwg(void)
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{
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return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
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}
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#define __read_mostly __attribute__((__section__(".data..read_mostly")))
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static inline int cache_line_size(void)
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{
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u32 cwg = cache_type_cwg();
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return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
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}
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/*
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* Read the effective value of CTR_EL0.
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*
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* According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
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* section D10.2.33 "CTR_EL0, Cache Type Register" :
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*
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* CTR_EL0.IDC reports the data cache clean requirements for
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* instruction to data coherence.
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*
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* 0 - dcache clean to PoU is required unless :
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* (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
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* 1 - dcache clean to PoU is not required for i-to-d coherence.
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*
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* This routine provides the CTR_EL0 with the IDC field updated to the
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* effective state.
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*/
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static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
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{
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u32 ctr = read_cpuid_cachetype();
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if (!(ctr & BIT(CTR_IDC_SHIFT))) {
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u64 clidr = read_sysreg(clidr_el1);
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if (CLIDR_LOC(clidr) == 0 ||
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(CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
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ctr |= BIT(CTR_IDC_SHIFT);
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}
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return ctr;
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}
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#endif /* __ASSEMBLY__ */
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#endif
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