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65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
198 lines
5.8 KiB
C
198 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2022 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt8186-clk.h>
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#include "clk-fhctl.h"
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#include "clk-mtk.h"
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#include "clk-pll.h"
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#include "clk-pllfh.h"
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#define MT8186_PLL_FMAX (3800UL * MHZ)
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#define MT8186_PLL_FMIN (1500UL * MHZ)
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#define MT8186_INTEGER_BITS (8)
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
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_rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
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_tuner_reg, _tuner_en_reg, _tuner_en_bit, \
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_pcw_reg) { \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = _rst_bar_mask, \
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.fmax = MT8186_PLL_FMAX, \
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.fmin = MT8186_PLL_FMIN, \
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.pcwbits = _pcwbits, \
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.pcwibits = MT8186_INTEGER_BITS, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = 0, \
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.pcw_chg_reg = 0, \
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.en_reg = 0, \
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.pll_en_bit = 0, \
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}
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static const struct mtk_pll_data plls[] = {
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/*
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* armpll_ll/armpll_bl/ccipll are main clock source of AP MCU,
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* should not be closed in Linux world.
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*/
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PLL(CLK_APMIXED_ARMPLL_LL, "armpll_ll", 0x0204, 0x0210, 0,
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PLL_AO, 0, 22, 0x0208, 24, 0, 0, 0, 0x0208),
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PLL(CLK_APMIXED_ARMPLL_BL, "armpll_bl", 0x0214, 0x0220, 0,
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PLL_AO, 0, 22, 0x0218, 24, 0, 0, 0, 0x0218),
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PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x0224, 0x0230, 0,
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PLL_AO, 0, 22, 0x0228, 24, 0, 0, 0, 0x0228),
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PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0244, 0x0250, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x0248, 24, 0, 0, 0, 0x0248),
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PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x0324, 0x0330, 0xff000000,
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HAVE_RST_BAR, BIT(23), 22, 0x0328, 24, 0, 0, 0, 0x0328),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x038C, 0x0398, 0,
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0, 0, 22, 0x0390, 24, 0, 0, 0, 0x0390),
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PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0254, 0x0260, 0,
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0, 0, 22, 0x0258, 24, 0, 0, 0, 0x0258),
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PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x035C, 0x0368, 0,
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0, 0, 22, 0x0360, 24, 0, 0, 0, 0x0360),
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PLL(CLK_APMIXED_NNA2PLL, "nna2pll", 0x036C, 0x0378, 0,
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0, 0, 22, 0x0370, 24, 0, 0, 0, 0x0370),
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PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x0304, 0x0310, 0,
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0, 0, 22, 0x0308, 24, 0, 0, 0, 0x0308),
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PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0314, 0x0320, 0,
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0, 0, 22, 0x0318, 24, 0, 0, 0, 0x0318),
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PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0264, 0x0270, 0,
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0, 0, 22, 0x0268, 24, 0, 0, 0, 0x0268),
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PLL(CLK_APMIXED_APLL1, "apll1", 0x0334, 0x0344, 0,
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0, 0, 32, 0x0338, 24, 0x0040, 0x000C, 0, 0x033C),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x0348, 0x0358, 0,
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0, 0, 32, 0x034C, 24, 0x0044, 0x000C, 5, 0x0350),
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};
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enum fh_pll_id {
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FH_ARMPLL_LL,
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FH_ARMPLL_BL,
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FH_CCIPLL,
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FH_MAINPLL,
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FH_MMPLL,
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FH_TVDPLL,
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FH_RESERVE6,
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FH_ADSPPLL,
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FH_MFGPLL,
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FH_NNAPLL,
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FH_NNA2PLL,
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FH_MSDCPLL,
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FH_RESERVE12,
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FH_NR_FH,
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};
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#define FH(_pllid, _fhid, _offset) { \
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.data = { \
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.pll_id = _pllid, \
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.fh_id = _fhid, \
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.fh_ver = FHCTL_PLLFH_V2, \
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.fhx_offset = _offset, \
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.dds_mask = GENMASK(21, 0), \
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.slope0_value = 0x6003c97, \
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.slope1_value = 0x6003c97, \
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.sfstrx_en = BIT(2), \
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.frddsx_en = BIT(1), \
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.fhctlx_en = BIT(0), \
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.tgl_org = BIT(31), \
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.dvfs_tri = BIT(31), \
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.pcwchg = BIT(31), \
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.dt_val = 0x0, \
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.df_val = 0x9, \
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.updnlmt_shft = 16, \
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.msk_frddsx_dys = GENMASK(23, 20), \
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.msk_frddsx_dts = GENMASK(19, 16), \
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}, \
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}
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static struct mtk_pllfh_data pllfhs[] = {
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FH(CLK_APMIXED_ARMPLL_LL, FH_ARMPLL_LL, 0x003C),
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FH(CLK_APMIXED_ARMPLL_BL, FH_ARMPLL_BL, 0x0050),
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FH(CLK_APMIXED_CCIPLL, FH_CCIPLL, 0x0064),
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FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x0078),
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FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0x008C),
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FH(CLK_APMIXED_TVDPLL, FH_TVDPLL, 0x00A0),
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FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x00C8),
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FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0x00DC),
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FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x00F0),
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FH(CLK_APMIXED_NNA2PLL, FH_NNA2PLL, 0x0104),
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FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x0118),
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};
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static const struct of_device_id of_match_clk_mt8186_apmixed[] = {
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{ .compatible = "mediatek,mt8186-apmixedsys", },
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{}
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8186_apmixed);
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static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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const u8 *fhctl_node = "mediatek,mt8186-fhctl";
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int r;
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clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
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r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
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pllfhs, ARRAY_SIZE(pllfhs), clk_data);
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if (r)
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goto free_apmixed_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_plls;
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platform_set_drvdata(pdev, clk_data);
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return r;
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unregister_plls:
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mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
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ARRAY_SIZE(pllfhs), clk_data);
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free_apmixed_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static int clk_mt8186_apmixed_remove(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
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ARRAY_SIZE(pllfhs), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt8186_apmixed_drv = {
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.probe = clk_mt8186_apmixed_probe,
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.remove = clk_mt8186_apmixed_remove,
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.driver = {
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.name = "clk-mt8186-apmixed",
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.of_match_table = of_match_clk_mt8186_apmixed,
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},
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};
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module_platform_driver(clk_mt8186_apmixed_drv);
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MODULE_LICENSE("GPL");
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