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Based on the normalized pattern:
this program is free software you can redistribute it and/or modify it
under the terms of the gnu general public license as published by the
free software foundation version 2 this program is distributed as is
without any warranty of any kind whether express or implied without
even the implied warranty of merchantability or fitness for a
particular purpose see the gnu general public license for more details
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference.
Reviewed-by: Allison Randal <allison@lohutok.net>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
305 lines
9.5 KiB
C
305 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2014 Broadcom Corporation
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/clkdev.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <dt-bindings/clock/bcm-cygnus.h>
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#include "clk-iproc.h"
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#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
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#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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.pwr_shift = ps, .iso_shift = is }
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#define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
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#define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
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{ .offset = o, .en_shift = es, .high_shift = hs, \
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.high_width = hw, .low_shift = ls, .low_width = lw }
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#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
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.p_reset_shift = prs }
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#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
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.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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.ka_width = kaw }
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#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
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#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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.hold_shift = hs, .bypass_shift = bs }
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#define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
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static void __init cygnus_armpll_init(struct device_node *node)
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{
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iproc_armpll_setup(node);
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}
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CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
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static const struct iproc_pll_ctrl genpll = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
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IPROC_CLK_PLL_NEEDS_SW_CFG,
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.aon = AON_VAL(0x0, 2, 1, 0),
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.reset = RESET_VAL(0x0, 11, 10),
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.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
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.sw_ctrl = SW_CTRL_VAL(0x10, 31),
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.ndiv_int = REG_VAL(0x10, 20, 10),
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.ndiv_frac = REG_VAL(0x10, 0, 20),
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.pdiv = REG_VAL(0x14, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
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.status = REG_VAL(0x28, 12, 1),
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};
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static const struct iproc_clk_ctrl genpll_clk[] = {
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[BCM_CYGNUS_GENPLL_AXI21_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 6, 0, 12),
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.mdiv = REG_VAL(0x20, 0, 8),
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},
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[BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 7, 1, 13),
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.mdiv = REG_VAL(0x20, 10, 8),
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},
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[BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 8, 2, 14),
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.mdiv = REG_VAL(0x20, 20, 8),
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},
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[BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 9, 3, 15),
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.mdiv = REG_VAL(0x24, 0, 8),
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},
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[BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 10, 4, 16),
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.mdiv = REG_VAL(0x24, 10, 8),
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},
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[BCM_CYGNUS_GENPLL_CAN_CLK] = {
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.channel = BCM_CYGNUS_GENPLL_CAN_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x4, 11, 5, 17),
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.mdiv = REG_VAL(0x24, 20, 8),
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},
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};
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static void __init cygnus_genpll_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
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ARRAY_SIZE(genpll_clk));
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}
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CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
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static const struct iproc_pll_ctrl lcpll0 = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
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.aon = AON_VAL(0x0, 2, 5, 4),
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.reset = RESET_VAL(0x0, 31, 30),
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.dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4),
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.sw_ctrl = SW_CTRL_VAL(0x4, 31),
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.ndiv_int = REG_VAL(0x4, 16, 10),
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.pdiv = REG_VAL(0x4, 26, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0x14),
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.status = REG_VAL(0x18, 12, 1),
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};
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static const struct iproc_clk_ctrl lcpll0_clk[] = {
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[BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 7, 1, 13),
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.mdiv = REG_VAL(0x8, 0, 8),
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},
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[BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 8, 2, 14),
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.mdiv = REG_VAL(0x8, 10, 8),
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},
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[BCM_CYGNUS_LCPLL0_SDIO_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 9, 3, 15),
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.mdiv = REG_VAL(0x8, 20, 8),
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},
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[BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 10, 4, 16),
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.mdiv = REG_VAL(0xc, 0, 8),
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},
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[BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = {
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.channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 11, 5, 17),
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.mdiv = REG_VAL(0xc, 10, 8),
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},
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[BCM_CYGNUS_LCPLL0_CH5_UNUSED] = {
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.channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 12, 6, 18),
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.mdiv = REG_VAL(0xc, 20, 8),
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},
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};
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static void __init cygnus_lcpll0_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
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ARRAY_SIZE(lcpll0_clk));
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}
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CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
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/*
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* MIPI PLL VCO frequency parameter table
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*/
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static const struct iproc_pll_vco_param mipipll_vco_params[] = {
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/* rate (Hz) ndiv_int ndiv_frac pdiv */
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{ 750000000UL, 30, 0, 1 },
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{ 1000000000UL, 40, 0, 1 },
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{ 1350000000ul, 54, 0, 1 },
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{ 2000000000UL, 80, 0, 1 },
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{ 2100000000UL, 84, 0, 1 },
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{ 2250000000UL, 90, 0, 1 },
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{ 2500000000UL, 100, 0, 1 },
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{ 2700000000UL, 54, 0, 0 },
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{ 2975000000UL, 119, 0, 1 },
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{ 3100000000UL, 124, 0, 1 },
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{ 3150000000UL, 126, 0, 1 },
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};
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static const struct iproc_pll_ctrl mipipll = {
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.flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC |
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IPROC_CLK_NEEDS_READ_BACK,
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.aon = AON_VAL(0x0, 4, 17, 16),
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.asiu = ASIU_GATE_VAL(0x0, 3),
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.reset = RESET_VAL(0x0, 11, 10),
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.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4),
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.ndiv_int = REG_VAL(0x10, 20, 10),
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.ndiv_frac = REG_VAL(0x10, 0, 20),
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.pdiv = REG_VAL(0x14, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
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.status = REG_VAL(0x28, 12, 1),
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};
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static const struct iproc_clk_ctrl mipipll_clk[] = {
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[BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = ENABLE_VAL(0x4, 12, 6, 18),
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.mdiv = REG_VAL(0x20, 0, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH1_LCD] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = ENABLE_VAL(0x4, 13, 7, 19),
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.mdiv = REG_VAL(0x20, 10, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH2_V3D] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = ENABLE_VAL(0x4, 14, 8, 20),
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.mdiv = REG_VAL(0x20, 20, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = ENABLE_VAL(0x4, 15, 9, 21),
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.mdiv = REG_VAL(0x24, 0, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = ENABLE_VAL(0x4, 16, 10, 22),
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.mdiv = REG_VAL(0x24, 10, 8),
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},
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[BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = {
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.channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
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.flags = IPROC_CLK_NEEDS_READ_BACK,
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.enable = ENABLE_VAL(0x4, 17, 11, 23),
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.mdiv = REG_VAL(0x24, 20, 8),
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},
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};
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static void __init cygnus_mipipll_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &mipipll, mipipll_vco_params,
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ARRAY_SIZE(mipipll_vco_params), mipipll_clk,
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ARRAY_SIZE(mipipll_clk));
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}
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CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
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static const struct iproc_asiu_div asiu_div[] = {
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[BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10),
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[BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10),
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[BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10),
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};
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static const struct iproc_asiu_gate asiu_gate[] = {
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[BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7),
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[BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9),
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[BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0),
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};
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static void __init cygnus_asiu_init(struct device_node *node)
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{
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iproc_asiu_setup(node, asiu_div, asiu_gate, ARRAY_SIZE(asiu_div));
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}
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CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
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static const struct iproc_pll_ctrl audiopll = {
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.flags = IPROC_CLK_PLL_NEEDS_SW_CFG | IPROC_CLK_PLL_HAS_NDIV_FRAC |
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IPROC_CLK_PLL_USER_MODE_ON | IPROC_CLK_PLL_RESET_ACTIVE_LOW |
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IPROC_CLK_PLL_CALC_PARAM,
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.reset = RESET_VAL(0x5c, 0, 1),
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.dig_filter = DF_VAL(0x48, 0, 3, 6, 4, 3, 3),
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.sw_ctrl = SW_CTRL_VAL(0x4, 0),
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.ndiv_int = REG_VAL(0x8, 0, 10),
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.ndiv_frac = REG_VAL(0x8, 10, 20),
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.pdiv = REG_VAL(0x44, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x0c, 0x10),
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.status = REG_VAL(0x54, 0, 1),
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.macro_mode = REG_VAL(0x0, 0, 3),
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};
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static const struct iproc_clk_ctrl audiopll_clk[] = {
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[BCM_CYGNUS_AUDIOPLL_CH0] = {
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.channel = BCM_CYGNUS_AUDIOPLL_CH0,
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.flags = IPROC_CLK_AON | IPROC_CLK_MCLK_DIV_BY_2,
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.enable = ENABLE_VAL(0x14, 8, 10, 9),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_CYGNUS_AUDIOPLL_CH1] = {
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.channel = BCM_CYGNUS_AUDIOPLL_CH1,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x18, 8, 10, 9),
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.mdiv = REG_VAL(0x18, 0, 8),
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},
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[BCM_CYGNUS_AUDIOPLL_CH2] = {
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.channel = BCM_CYGNUS_AUDIOPLL_CH2,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x1c, 8, 10, 9),
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.mdiv = REG_VAL(0x1c, 0, 8),
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},
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};
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static void __init cygnus_audiopll_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &audiopll, NULL, 0,
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audiopll_clk, ARRAY_SIZE(audiopll_clk));
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}
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CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",
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cygnus_audiopll_clk_init);
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