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On OMAP4+ devices, GIC register context is lost when MPUSS hits
the OSWR(Open Switch Retention). On the CPU wakeup path, ROM code
gets executed and one of the steps in it is to restore the
saved context of the GIC. The ROM Code GIC distributor restoration
is split in two parts: CPU specific register done by each CPU and
common register done by only one CPU.
Below is the abstract flow.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[...]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU0 is online in OS
- CPU0 enables the GIC distributor. GICD.Enable Non-secure = 1
- CPU0 wakes up CPU1 with clock-domain force wakeup method.
- CPU0 continues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[...]
- CPU1 is online in OS and start executing.
[...] -
GIC Restoration: /* Common routine for HS and GP devices */
{
if (GICD != 1) { /* This will be true in OSWR state */
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restores GIC distributor
else
- reconfigure GIC distributor to boot values.
GICD.Enable secure = 1
}
if (GIC_SAR_BACKUP_STATE == SAVED)
- CPU restore its GIC CPU interface registers if saved.
else
- reconfigure its GIC CPU interface registers to boot
values.
}
...............................................................
So as mentioned in the flow, GICD != 1 condition decides how
the GIC registers are handled in ROM code wakeup path from
OSWR. As evident from the flow, ROM code relies on the entire
GICD register value and not specific register bits.
The assumption was valid till CortexA9 r1pX version since there
was only one banked bit to control secure and non-secure GICD.
Secure view which ROM code sees:
bit 0 == Enable Non-secure
Non-secure view which HLOS sees:
bit 0 == Enable secure
But GICD register has changed between CortexA9 r1pX and r2pX.
On r2pX GICD register is composed of 2 bits.
Secure view which ROM code sees:
bit 1 == Enable Non-secure
bit 0 == Enable secure
Non-secure view which HLOS sees:
bit 0 == Enable Non-secure
Hence on OMAP4460(r2pX) devices, if you go through the
above flow again during CPU1 wakeup, GICD == 3 and hence
ROM code fails to understand the real wakeup power state
and reconfigures GIC distributor to boot values. This is
nasty since you loose the entire interrupt controller
context in a live system.
The ROM code fix done on next OMAP4 device (OMAP4470 - r2px) is to
check "GICD.Enable secure != 1" for GIC restoration in OSWR wakeup path.
Since ROM code can't be fixed on OMAP4460 devices, a work around
needs to be implemented. As evident from the flow, as long as
CPU1 sees GICD == 1 in it's wakeup path from OSWR, the issue
won't happen. Below is the flow with the work-around.
...............................................................
- MPUSS in OSWR state.
- CPU0 wakes up on the event(interrupt) and start executing ROM code.
[..]
- CPU0 executes "GIC Restoration:"
[..]
- CPU0 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU0 is online in OS.
- CPU0 does GICD.Enable Non-secure = 0
- CPU0 wakes up CPU1 with clock domain force wakeup method.
- CPU0 waits for GICD.Enable Non-secure = 1
- CPU0 coninues it's execution.
[..]
- CPU1 wakes up and start executing ROM code.
[..]
- CPU1 executes "GIC Restoration:"
[..]
- CPU1 swicthes to non-secure mode and jumps to OS resume code.
[..]
- CPU1 is online in OS
- CPU1 does GICD.Enable Non-secure = 1
- CPU1 start executing
[...]
...............................................................
With this procedure, the GIC configuration done between the
CPU0 wakeup and CPU1 wakeup will not be lost but during this
short windows, the CPU0 will not receive interrupts.
The BUG is applicable to only OMAP4460(r2pX) devices.
OMAP4470 (also r2pX) is not affected by this bug because
ROM code has been fixed.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
105 lines
2.8 KiB
ArmAsm
105 lines
2.8 KiB
ArmAsm
/*
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* Secondary CPU startup routine source file.
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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*
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* Author:
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* Interface functions needed for the SMP. This file is based on arm
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* realview smp platform.
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* Copyright (c) 2003 ARM Limited.
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*
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* This program is free software,you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include "omap44xx.h"
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__CPUINIT
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/* Physical address needed since MMU not enabled yet on secondary core */
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#define AUX_CORE_BOOT0_PA 0x48281800
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/*
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* OMAP5 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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* secondary core is held until we're ready for it to initialise.
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* The primary core will update this flag using a hardware
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+ * register AuxCoreBoot0.
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*/
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ENTRY(omap5_secondary_startup)
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wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0
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ldr r0, [r2]
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mov r0, r0, lsr #5
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne wait
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b secondary_startup
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END(omap5_secondary_startup)
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/*
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* OMAP4 specific entry point for secondary CPU to jump from ROM
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* code. This routine also provides a holding flag into which
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* secondary core is held until we're ready for it to initialise.
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* The primary core will update this flag using a hardware
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* register AuxCoreBoot0.
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*/
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ENTRY(omap_secondary_startup)
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hold: ldr r12,=0x103
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dsb
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smc #0 @ read from AuxCoreBoot0
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mov r0, r0, lsr #9
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne hold
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/*
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* we've been released from the wait loop,secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(omap_secondary_startup)
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ENTRY(omap_secondary_startup_4460)
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hold_2: ldr r12,=0x103
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dsb
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smc #0 @ read from AuxCoreBoot0
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mov r0, r0, lsr #9
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mrc p15, 0, r4, c0, c0, 5
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and r4, r4, #0x0f
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cmp r0, r4
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bne hold_2
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/*
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* GIC distributor control register has changed between
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* CortexA9 r1pX and r2pX. The Control Register secure
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* banked version is now composed of 2 bits:
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* bit 0 == Secure Enable
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* bit 1 == Non-Secure Enable
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* The Non-Secure banked register has not changed
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* Because the ROM Code is based on the r1pX GIC, the CPU1
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* GIC restoration will cause a problem to CPU0 Non-Secure SW.
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* The workaround must be:
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* 1) Before doing the CPU1 wakeup, CPU0 must disable
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* the GIC distributor
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* 2) CPU1 must re-enable the GIC distributor on
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* it's wakeup path.
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*/
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ldr r1, =OMAP44XX_GIC_DIST_BASE
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ldr r0, [r1]
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orr r0, #1
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str r0, [r1]
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/*
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* we've been released from the wait loop,secondary_stack
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* should now contain the SVC stack for this core
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*/
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b secondary_startup
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ENDPROC(omap_secondary_startup_4460)
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