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63111a3a70
There's no need to iterative over every single irq_desc when we can already work out which IRQs have a backing descriptor via the shiny new for_each_active_irq(). Switch to that instead. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
483 lines
12 KiB
C
483 lines
12 KiB
C
/*
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* Shared interrupt handling code for IPR and INTC2 types of IRQs.
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*
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* Copyright (C) 2007, 2008 Magnus Damm
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* Copyright (C) 2009, 2010 Paul Mundt
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*
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* Based on intc2.c and ipr.c
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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* Copyright (C) 2005, 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define pr_fmt(fmt) "intc: " fmt
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/sh_intc.h>
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#include <linux/sysdev.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/radix-tree.h>
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#include "internals.h"
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LIST_HEAD(intc_list);
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DEFINE_RAW_SPINLOCK(intc_big_lock);
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unsigned int nr_intc_controllers;
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/*
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* Default priority level
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* - this needs to be at least 2 for 5-bit priorities on 7780
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*/
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static unsigned int default_prio_level = 2; /* 2 - 16 */
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static unsigned int intc_prio_level[NR_IRQS]; /* for now */
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unsigned int intc_get_dfl_prio_level(void)
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{
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return default_prio_level;
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}
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unsigned int intc_get_prio_level(unsigned int irq)
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{
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return intc_prio_level[irq];
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}
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void intc_set_prio_level(unsigned int irq, unsigned int level)
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{
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unsigned long flags;
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raw_spin_lock_irqsave(&intc_big_lock, flags);
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intc_prio_level[irq] = level;
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raw_spin_unlock_irqrestore(&intc_big_lock, flags);
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}
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static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc)
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{
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generic_handle_irq((unsigned int)get_irq_data(irq));
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}
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static void __init intc_register_irq(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id,
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unsigned int irq)
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{
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struct intc_handle_int *hp;
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struct irq_data *irq_data;
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unsigned int data[2], primary;
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unsigned long flags;
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/*
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* Register the IRQ position with the global IRQ map, then insert
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* it in to the radix tree.
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*/
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irq_reserve_irqs(irq, 1);
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raw_spin_lock_irqsave(&intc_big_lock, flags);
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radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
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raw_spin_unlock_irqrestore(&intc_big_lock, flags);
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/*
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* Prefer single interrupt source bitmap over other combinations:
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*
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* 1. bitmap, single interrupt source
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* 2. priority, single interrupt source
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* 3. bitmap, multiple interrupt sources (groups)
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* 4. priority, multiple interrupt sources (groups)
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*/
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data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
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data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
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primary = 0;
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if (!data[0] && data[1])
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primary = 1;
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if (!data[0] && !data[1])
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pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n",
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irq, irq2evt(irq));
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data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
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data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
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if (!data[primary])
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primary ^= 1;
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BUG_ON(!data[primary]); /* must have primary masking method */
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irq_data = irq_get_irq_data(irq);
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disable_irq_nosync(irq);
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set_irq_chip_and_handler_name(irq, &d->chip,
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handle_level_irq, "level");
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set_irq_chip_data(irq, (void *)data[primary]);
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/*
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* set priority level
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*/
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intc_set_prio_level(irq, intc_get_dfl_prio_level());
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/* enable secondary masking method if present */
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if (data[!primary])
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_intc_enable(irq_data, data[!primary]);
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/* add irq to d->prio list if priority is available */
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if (data[1]) {
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hp = d->prio + d->nr_prio;
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hp->irq = irq;
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hp->handle = data[1];
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if (primary) {
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/*
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* only secondary priority should access registers, so
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* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
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*/
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hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
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hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
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}
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d->nr_prio++;
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}
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/* add irq to d->sense list if sense is available */
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data[0] = intc_get_sense_handle(desc, d, enum_id);
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if (data[0]) {
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(d->sense + d->nr_sense)->irq = irq;
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(d->sense + d->nr_sense)->handle = data[0];
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d->nr_sense++;
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}
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/* irq should be disabled by default */
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d->chip.irq_mask(irq_data);
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intc_set_ack_handle(irq, desc, d, enum_id);
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intc_set_dist_handle(irq, desc, d, enum_id);
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activate_irq(irq);
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}
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static unsigned int __init save_reg(struct intc_desc_int *d,
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unsigned int cnt,
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unsigned long value,
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unsigned int smp)
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{
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if (value) {
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value = intc_phys_to_virt(d, value);
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d->reg[cnt] = value;
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#ifdef CONFIG_SMP
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d->smp[cnt] = smp;
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#endif
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return 1;
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}
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return 0;
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}
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int __init register_intc_controller(struct intc_desc *desc)
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{
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unsigned int i, k, smp;
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struct intc_hw_desc *hw = &desc->hw;
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struct intc_desc_int *d;
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struct resource *res;
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pr_info("Registered controller '%s' with %u IRQs\n",
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desc->name, hw->nr_vectors);
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d = kzalloc(sizeof(*d), GFP_NOWAIT);
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if (!d)
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goto err0;
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INIT_LIST_HEAD(&d->list);
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list_add_tail(&d->list, &intc_list);
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raw_spin_lock_init(&d->lock);
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d->index = nr_intc_controllers;
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if (desc->num_resources) {
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d->nr_windows = desc->num_resources;
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d->window = kzalloc(d->nr_windows * sizeof(*d->window),
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GFP_NOWAIT);
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if (!d->window)
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goto err1;
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for (k = 0; k < d->nr_windows; k++) {
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res = desc->resource + k;
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WARN_ON(resource_type(res) != IORESOURCE_MEM);
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d->window[k].phys = res->start;
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d->window[k].size = resource_size(res);
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d->window[k].virt = ioremap_nocache(res->start,
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resource_size(res));
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if (!d->window[k].virt)
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goto err2;
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}
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}
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d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
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#ifdef CONFIG_INTC_BALANCING
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if (d->nr_reg)
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d->nr_reg += hw->nr_mask_regs;
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#endif
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d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
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d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
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d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
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d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
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d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
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if (!d->reg)
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goto err2;
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#ifdef CONFIG_SMP
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d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT);
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if (!d->smp)
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goto err3;
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#endif
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k = 0;
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if (hw->mask_regs) {
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for (i = 0; i < hw->nr_mask_regs; i++) {
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smp = IS_SMP(hw->mask_regs[i]);
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k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
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k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
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#ifdef CONFIG_INTC_BALANCING
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k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
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#endif
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}
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}
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if (hw->prio_regs) {
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d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
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GFP_NOWAIT);
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if (!d->prio)
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goto err4;
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for (i = 0; i < hw->nr_prio_regs; i++) {
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smp = IS_SMP(hw->prio_regs[i]);
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k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
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k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
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}
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}
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if (hw->sense_regs) {
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d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
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GFP_NOWAIT);
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if (!d->sense)
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goto err5;
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for (i = 0; i < hw->nr_sense_regs; i++)
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k += save_reg(d, k, hw->sense_regs[i].reg, 0);
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}
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if (hw->subgroups)
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for (i = 0; i < hw->nr_subgroups; i++)
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if (hw->subgroups[i].reg)
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k+= save_reg(d, k, hw->subgroups[i].reg, 0);
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memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
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d->chip.name = desc->name;
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if (hw->ack_regs)
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for (i = 0; i < hw->nr_ack_regs; i++)
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k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
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else
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d->chip.irq_mask_ack = d->chip.irq_disable;
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/* disable bits matching force_disable before registering irqs */
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if (desc->force_disable)
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intc_enable_disable_enum(desc, d, desc->force_disable, 0);
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/* disable bits matching force_enable before registering irqs */
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if (desc->force_enable)
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intc_enable_disable_enum(desc, d, desc->force_enable, 0);
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BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
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/* register the vectors one by one */
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for (i = 0; i < hw->nr_vectors; i++) {
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struct intc_vect *vect = hw->vectors + i;
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unsigned int irq = evt2irq(vect->vect);
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int res;
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if (!vect->enum_id)
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continue;
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res = irq_alloc_desc_at(irq, numa_node_id());
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if (res != irq && res != -EEXIST) {
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pr_err("can't get irq_desc for %d\n", irq);
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continue;
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}
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intc_irq_xlate_set(irq, vect->enum_id, d);
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intc_register_irq(desc, d, vect->enum_id, irq);
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for (k = i + 1; k < hw->nr_vectors; k++) {
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struct intc_vect *vect2 = hw->vectors + k;
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unsigned int irq2 = evt2irq(vect2->vect);
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if (vect->enum_id != vect2->enum_id)
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continue;
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/*
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* In the case of multi-evt handling and sparse
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* IRQ support, each vector still needs to have
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* its own backing irq_desc.
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*/
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res = irq_alloc_desc_at(irq2, numa_node_id());
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if (res != irq2 && res != -EEXIST) {
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pr_err("can't get irq_desc for %d\n", irq2);
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continue;
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}
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vect2->enum_id = 0;
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/* redirect this interrupts to the first one */
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set_irq_chip(irq2, &dummy_irq_chip);
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set_irq_chained_handler(irq2, intc_redirect_irq);
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set_irq_data(irq2, (void *)irq);
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}
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}
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intc_subgroup_init(desc, d);
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/* enable bits matching force_enable after registering irqs */
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if (desc->force_enable)
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intc_enable_disable_enum(desc, d, desc->force_enable, 1);
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nr_intc_controllers++;
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return 0;
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err5:
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kfree(d->prio);
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err4:
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#ifdef CONFIG_SMP
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kfree(d->smp);
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err3:
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#endif
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kfree(d->reg);
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err2:
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for (k = 0; k < d->nr_windows; k++)
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if (d->window[k].virt)
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iounmap(d->window[k].virt);
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kfree(d->window);
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err1:
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kfree(d);
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err0:
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pr_err("unable to allocate INTC memory\n");
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return -ENOMEM;
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}
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static ssize_t
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show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf)
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{
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struct intc_desc_int *d;
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d = container_of(dev, struct intc_desc_int, sysdev);
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return sprintf(buf, "%s\n", d->chip.name);
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}
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static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL);
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static int intc_suspend(struct sys_device *dev, pm_message_t state)
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{
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struct intc_desc_int *d;
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struct irq_data *data;
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struct irq_desc *desc;
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struct irq_chip *chip;
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int irq;
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/* get intc controller associated with this sysdev */
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d = container_of(dev, struct intc_desc_int, sysdev);
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switch (state.event) {
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case PM_EVENT_ON:
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if (d->state.event != PM_EVENT_FREEZE)
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break;
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for_each_active_irq(irq) {
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desc = irq_to_desc(irq);
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data = irq_get_irq_data(irq);
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chip = irq_data_get_irq_chip(data);
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/*
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* This will catch the redirect and VIRQ cases
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* due to the dummy_irq_chip being inserted.
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*/
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if (chip != &d->chip)
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continue;
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if (desc->status & IRQ_DISABLED)
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chip->irq_disable(data);
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else
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chip->irq_enable(data);
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}
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break;
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case PM_EVENT_FREEZE:
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/* nothing has to be done */
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break;
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case PM_EVENT_SUSPEND:
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/* enable wakeup irqs belonging to this intc controller */
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for_each_active_irq(irq) {
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desc = irq_to_desc(irq);
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data = irq_get_irq_data(irq);
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chip = irq_data_get_irq_chip(data);
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if (chip != &d->chip)
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continue;
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if ((desc->status & IRQ_WAKEUP))
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chip->irq_enable(data);
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}
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break;
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}
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d->state = state;
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return 0;
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}
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static int intc_resume(struct sys_device *dev)
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{
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return intc_suspend(dev, PMSG_ON);
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}
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struct sysdev_class intc_sysdev_class = {
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.name = "intc",
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.suspend = intc_suspend,
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.resume = intc_resume,
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};
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/* register this intc as sysdev to allow suspend/resume */
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static int __init register_intc_sysdevs(void)
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{
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struct intc_desc_int *d;
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int error;
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error = sysdev_class_register(&intc_sysdev_class);
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if (!error) {
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list_for_each_entry(d, &intc_list, list) {
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d->sysdev.id = d->index;
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d->sysdev.cls = &intc_sysdev_class;
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error = sysdev_register(&d->sysdev);
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if (error == 0)
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error = sysdev_create_file(&d->sysdev,
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&attr_name);
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if (error)
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break;
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}
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}
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if (error)
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pr_err("sysdev registration error\n");
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return error;
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}
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device_initcall(register_intc_sysdevs);
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