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e6c7e6216d
The difference between MT8186 and other ICs is that when modifying the
output format, we need to modify the mmsys_base+0x400 register to take
effect. So when setting the dpi output format, we need to call
mtk_mmsys_ddp_dpi_fmt_config to set it to MT8186 synchronously.
Commit a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi
output for MT8186") lacked some of the possible output formats and also
had a wrong bitmask.
Add the missing output formats and fix the bitmask.
While at it, also update mtk_mmsys_ddp_dpi_fmt_config() to use generic
formats, so that it is slightly easier to extend for other platforms.
Fixes: a071e52f75d1 ("soc: mediatek: Add mmsys func to adapt to dpi output for MT8186")
Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
124 lines
3.9 KiB
C
124 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
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#define __SOC_MEDIATEK_MT8186_MMSYS_H
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/* Values for DPI configuration in MMSYS address space */
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#define MT8186_MMSYS_DPI_OUTPUT_FORMAT 0x400
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#define MT8186_DPI_FORMAT_MASK GENMASK(1, 0)
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#define MT8186_DPI_RGB888_SDR_CON 0
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#define MT8186_DPI_RGB888_DDR_CON 1
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#define MT8186_DPI_RGB565_SDR_CON 2
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#define MT8186_DPI_RGB565_DDR_CON 3
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#define MT8186_MMSYS_OVL_CON 0xF04
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#define MT8186_MMSYS_OVL0_CON_MASK 0x3
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#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
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#define MT8186_OVL0_GO_BLEND BIT(0)
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#define MT8186_OVL0_GO_BG BIT(1)
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#define MT8186_OVL0_2L_GO_BLEND BIT(2)
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#define MT8186_OVL0_2L_GO_BG BIT(3)
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#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
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#define MT8186_RDMA0_SOUT_SEL_MASK 0xF
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#define MT8186_RDMA0_SOUT_TO_DSI0 (0)
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#define MT8186_RDMA0_SOUT_TO_COLOR0 (1)
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#define MT8186_RDMA0_SOUT_TO_DPI0 (2)
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#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14
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#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF
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#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)
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#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)
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#define MT8186_DISP_OVL0_MOUT_EN 0xF18
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#define MT8186_OVL0_MOUT_EN_MASK 0xF
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#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)
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#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)
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#define MT8186_DISP_DITHER0_MOUT_EN 0xF20
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#define MT8186_DITHER0_MOUT_EN_MASK 0xF
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#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)
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#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)
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#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)
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#define MT8186_DISP_RDMA0_SEL_IN 0xF28
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#define MT8186_RDMA0_SEL_IN_MASK 0xF
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#define MT8186_RDMA0_FROM_OVL0 0
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#define MT8186_RDMA0_FROM_OVL0_2L 2
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#define MT8186_DISP_DSI0_SEL_IN 0xF30
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#define MT8186_DSI0_SEL_IN_MASK 0xF
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#define MT8186_DSI0_FROM_RDMA0 0
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#define MT8186_DSI0_FROM_DITHER0 1
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#define MT8186_DSI0_FROM_RDMA1 2
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#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C
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#define MT8186_RDMA1_MOUT_EN_MASK 0xF
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#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)
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#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)
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#define MT8186_DISP_RDMA1_SEL_IN 0xF40
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#define MT8186_RDMA1_SEL_IN_MASK 0xF
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#define MT8186_RDMA1_FROM_OVL0 0
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#define MT8186_RDMA1_FROM_OVL0_2L 2
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#define MT8186_RDMA1_FROM_DITHER0 3
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#define MT8186_DISP_DPI0_SEL_IN 0xF44
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#define MT8186_DPI0_SEL_IN_MASK 0xF
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#define MT8186_DPI0_FROM_RDMA1 0
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#define MT8186_DPI0_FROM_DITHER0 1
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#define MT8186_DPI0_FROM_RDMA0 2
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#define MT8186_MMSYS_SW0_RST_B 0x160
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static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
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MT8186_OVL0_MOUT_TO_RDMA0
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},
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
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MT8186_RDMA0_FROM_OVL0
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},
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
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MT8186_OVL0_GO_BLEND
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},
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{
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
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MT8186_RDMA0_SOUT_TO_COLOR0
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},
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{
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
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MT8186_DITHER0_MOUT_TO_DSI0,
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},
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{
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
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MT8186_DSI0_FROM_DITHER0
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},
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{
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
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MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
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MT8186_OVL0_2L_MOUT_TO_RDMA1
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},
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{
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
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MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
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MT8186_RDMA1_FROM_OVL0_2L
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},
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{
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DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
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MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
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MT8186_OVL0_2L_GO_BLEND
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},
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{
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
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MT8186_RDMA1_MOUT_TO_DPI0_SEL
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},
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{
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
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MT8186_DPI0_FROM_RDMA1
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},
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};
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#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */
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