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Implements OPAL RTC and NVRAM support and wire all that up to the powernv platform. We use RTAS for RTC as a fallback if available. Using RTAS for nvram is not supported yet, pending some rework/cleanup and generalization of the pSeries & CHRP code. We also use RTAS fallbacks for power off and reboot Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
442 lines
14 KiB
C
442 lines
14 KiB
C
/*
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* PowerNV OPAL definitions.
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*
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* Copyright 2011 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __OPAL_H
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#define __OPAL_H
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/****** Takeover interface ********/
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/* PAPR H-Call used to querty the HAL existence and/or instanciate
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* it from within pHyp (tech preview only).
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*
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* This is exclusively used in prom_init.c
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*/
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#ifndef __ASSEMBLY__
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struct opal_takeover_args {
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u64 k_image; /* r4 */
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u64 k_size; /* r5 */
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u64 k_entry; /* r6 */
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u64 k_entry2; /* r7 */
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u64 hal_addr; /* r8 */
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u64 rd_image; /* r9 */
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u64 rd_size; /* r10 */
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u64 rd_loc; /* r11 */
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};
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extern long opal_query_takeover(u64 *hal_size, u64 *hal_align);
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extern long opal_do_takeover(struct opal_takeover_args *args);
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struct rtas_args;
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extern int opal_enter_rtas(struct rtas_args *args,
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unsigned long data,
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unsigned long entry);
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#endif /* __ASSEMBLY__ */
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/****** OPAL APIs ******/
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/* Return codes */
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#define OPAL_SUCCESS 0
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#define OPAL_PARAMETER -1
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#define OPAL_BUSY -2
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#define OPAL_PARTIAL -3
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#define OPAL_CONSTRAINED -4
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#define OPAL_CLOSED -5
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#define OPAL_HARDWARE -6
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#define OPAL_UNSUPPORTED -7
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#define OPAL_PERMISSION -8
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#define OPAL_NO_MEM -9
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#define OPAL_RESOURCE -10
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#define OPAL_INTERNAL_ERROR -11
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#define OPAL_BUSY_EVENT -12
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#define OPAL_HARDWARE_FROZEN -13
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/* API Tokens (in r0) */
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#define OPAL_CONSOLE_WRITE 1
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#define OPAL_CONSOLE_READ 2
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#define OPAL_RTC_READ 3
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#define OPAL_RTC_WRITE 4
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#define OPAL_CEC_POWER_DOWN 5
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#define OPAL_CEC_REBOOT 6
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#define OPAL_READ_NVRAM 7
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#define OPAL_WRITE_NVRAM 8
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#define OPAL_HANDLE_INTERRUPT 9
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#define OPAL_POLL_EVENTS 10
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#define OPAL_PCI_SET_HUB_TCE_MEMORY 11
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#define OPAL_PCI_SET_PHB_TCE_MEMORY 12
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#define OPAL_PCI_CONFIG_READ_BYTE 13
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#define OPAL_PCI_CONFIG_READ_HALF_WORD 14
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#define OPAL_PCI_CONFIG_READ_WORD 15
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#define OPAL_PCI_CONFIG_WRITE_BYTE 16
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#define OPAL_PCI_CONFIG_WRITE_HALF_WORD 17
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#define OPAL_PCI_CONFIG_WRITE_WORD 18
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#define OPAL_SET_XIVE 19
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#define OPAL_GET_XIVE 20
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#define OPAL_GET_COMPLETION_TOKEN_STATUS 21 /* obsolete */
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#define OPAL_REGISTER_OPAL_EXCEPTION_HANDLER 22
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#define OPAL_PCI_EEH_FREEZE_STATUS 23
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#define OPAL_PCI_SHPC 24
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#define OPAL_CONSOLE_WRITE_BUFFER_SPACE 25
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#define OPAL_PCI_EEH_FREEZE_CLEAR 26
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#define OPAL_PCI_PHB_MMIO_ENABLE 27
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#define OPAL_PCI_SET_PHB_MEM_WINDOW 28
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#define OPAL_PCI_MAP_PE_MMIO_WINDOW 29
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#define OPAL_PCI_SET_PHB_TABLE_MEMORY 30
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#define OPAL_PCI_SET_PE 31
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#define OPAL_PCI_SET_PELTV 32
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#define OPAL_PCI_SET_MVE 33
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#define OPAL_PCI_SET_MVE_ENABLE 34
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#define OPAL_PCI_GET_XIVE_REISSUE 35
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#define OPAL_PCI_SET_XIVE_REISSUE 36
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#define OPAL_PCI_SET_XIVE_PE 37
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#define OPAL_GET_XIVE_SOURCE 38
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#define OPAL_GET_MSI_32 39
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#define OPAL_GET_MSI_64 40
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#define OPAL_START_CPU 41
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#define OPAL_QUERY_CPU_STATUS 42
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#define OPAL_WRITE_OPPANEL 43
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#define OPAL_PCI_MAP_PE_DMA_WINDOW 44
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#define OPAL_PCI_MAP_PE_DMA_WINDOW_REAL 45
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#define OPAL_PCI_RESET 49
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#ifndef __ASSEMBLY__
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/* Other enums */
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enum OpalVendorApiTokens {
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OPAL_START_VENDOR_API_RANGE = 1000, OPAL_END_VENDOR_API_RANGE = 1999
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};
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enum OpalFreezeState {
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OPAL_EEH_STOPPED_NOT_FROZEN = 0,
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OPAL_EEH_STOPPED_MMIO_FREEZE = 1,
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OPAL_EEH_STOPPED_DMA_FREEZE = 2,
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OPAL_EEH_STOPPED_MMIO_DMA_FREEZE = 3,
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OPAL_EEH_STOPPED_RESET = 4,
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OPAL_EEH_STOPPED_TEMP_UNAVAIL = 5,
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OPAL_EEH_STOPPED_PERM_UNAVAIL = 6
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};
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enum OpalEehFreezeActionToken {
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OPAL_EEH_ACTION_CLEAR_FREEZE_MMIO = 1,
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OPAL_EEH_ACTION_CLEAR_FREEZE_DMA = 2,
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OPAL_EEH_ACTION_CLEAR_FREEZE_ALL = 3
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};
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enum OpalPciStatusToken {
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OPAL_EEH_PHB_NO_ERROR = 0,
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OPAL_EEH_PHB_FATAL = 1,
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OPAL_EEH_PHB_RECOVERABLE = 2,
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OPAL_EEH_PHB_BUS_ERROR = 3,
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OPAL_EEH_PCI_NO_DEVSEL = 4,
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OPAL_EEH_PCI_TA = 5,
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OPAL_EEH_PCIEX_UR = 6,
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OPAL_EEH_PCIEX_CA = 7,
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OPAL_EEH_PCI_MMIO_ERROR = 8,
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OPAL_EEH_PCI_DMA_ERROR = 9
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};
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enum OpalShpcAction {
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OPAL_SHPC_GET_LINK_STATE = 0,
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OPAL_SHPC_GET_SLOT_STATE = 1
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};
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enum OpalShpcLinkState {
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OPAL_SHPC_LINK_DOWN = 0,
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OPAL_SHPC_LINK_UP = 1
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};
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enum OpalMmioWindowType {
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OPAL_M32_WINDOW_TYPE = 1,
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OPAL_M64_WINDOW_TYPE = 2,
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OPAL_IO_WINDOW_TYPE = 3
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};
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enum OpalShpcSlotState {
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OPAL_SHPC_DEV_NOT_PRESENT = 0,
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OPAL_SHPC_DEV_PRESENT = 1
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};
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enum OpalExceptionHandler {
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OPAL_MACHINE_CHECK_HANDLER = 1,
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OPAL_HYPERVISOR_MAINTENANCE_HANDLER = 2,
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OPAL_SOFTPATCH_HANDLER = 3
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};
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enum OpalPendingState {
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OPAL_EVENT_OPAL_INTERNAL = 0x1,
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OPAL_EVENT_NVRAM = 0x2,
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OPAL_EVENT_RTC = 0x4,
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OPAL_EVENT_CONSOLE_OUTPUT = 0x8,
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OPAL_EVENT_CONSOLE_INPUT = 0x10
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};
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/* Machine check related definitions */
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enum OpalMCE_Version {
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OpalMCE_V1 = 1,
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};
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enum OpalMCE_Severity {
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OpalMCE_SEV_NO_ERROR = 0,
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OpalMCE_SEV_WARNING = 1,
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OpalMCE_SEV_ERROR_SYNC = 2,
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OpalMCE_SEV_FATAL = 3,
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};
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enum OpalMCE_Disposition {
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OpalMCE_DISPOSITION_RECOVERED = 0,
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OpalMCE_DISPOSITION_NOT_RECOVERED = 1,
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};
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enum OpalMCE_Initiator {
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OpalMCE_INITIATOR_UNKNOWN = 0,
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OpalMCE_INITIATOR_CPU = 1,
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};
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enum OpalMCE_ErrorType {
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OpalMCE_ERROR_TYPE_UNKNOWN = 0,
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OpalMCE_ERROR_TYPE_UE = 1,
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OpalMCE_ERROR_TYPE_SLB = 2,
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OpalMCE_ERROR_TYPE_ERAT = 3,
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OpalMCE_ERROR_TYPE_TLB = 4,
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};
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enum OpalMCE_UeErrorType {
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OpalMCE_UE_ERROR_INDETERMINATE = 0,
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OpalMCE_UE_ERROR_IFETCH = 1,
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OpalMCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
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OpalMCE_UE_ERROR_LOAD_STORE = 3,
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OpalMCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
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};
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enum OpalMCE_SlbErrorType {
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OpalMCE_SLB_ERROR_INDETERMINATE = 0,
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OpalMCE_SLB_ERROR_PARITY = 1,
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OpalMCE_SLB_ERROR_MULTIHIT = 2,
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};
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enum OpalMCE_EratErrorType {
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OpalMCE_ERAT_ERROR_INDETERMINATE = 0,
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OpalMCE_ERAT_ERROR_PARITY = 1,
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OpalMCE_ERAT_ERROR_MULTIHIT = 2,
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};
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enum OpalMCE_TlbErrorType {
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OpalMCE_TLB_ERROR_INDETERMINATE = 0,
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OpalMCE_TLB_ERROR_PARITY = 1,
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OpalMCE_TLB_ERROR_MULTIHIT = 2,
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};
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enum OpalThreadStatus {
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OPAL_THREAD_INACTIVE = 0x0,
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OPAL_THREAD_STARTED = 0x1
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};
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enum OpalPciBusCompare {
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OpalPciBusAny = 0, /* Any bus number match */
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OpalPciBus3Bits = 2, /* Match top 3 bits of bus number */
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OpalPciBus4Bits = 3, /* Match top 4 bits of bus number */
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OpalPciBus5Bits = 4, /* Match top 5 bits of bus number */
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OpalPciBus6Bits = 5, /* Match top 6 bits of bus number */
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OpalPciBus7Bits = 6, /* Match top 7 bits of bus number */
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OpalPciBusAll = 7, /* Match bus number exactly */
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};
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enum OpalDeviceCompare {
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OPAL_IGNORE_RID_DEVICE_NUMBER = 0,
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OPAL_COMPARE_RID_DEVICE_NUMBER = 1
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};
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enum OpalFuncCompare {
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OPAL_IGNORE_RID_FUNCTION_NUMBER = 0,
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OPAL_COMPARE_RID_FUNCTION_NUMBER = 1
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};
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enum OpalPeAction {
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OPAL_UNMAP_PE = 0,
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OPAL_MAP_PE = 1
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};
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enum OpalPciResetAndReinitScope {
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OPAL_PHB_COMPLETE = 1, OPAL_PCI_LINK = 2, OPAL_PHB_ERROR = 3,
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OPAL_PCI_HOT_RESET = 4, OPAL_PCI_FUNDAMENTAL_RESET = 5,
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OPAL_PCI_IODA_RESET = 6,
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};
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enum OpalPciResetState { OPAL_DEASSERT_RESET = 0, OPAL_ASSERT_RESET = 1 };
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struct opal_machine_check_event {
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enum OpalMCE_Version version:8; /* 0x00 */
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uint8_t in_use; /* 0x01 */
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enum OpalMCE_Severity severity:8; /* 0x02 */
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enum OpalMCE_Initiator initiator:8; /* 0x03 */
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enum OpalMCE_ErrorType error_type:8; /* 0x04 */
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enum OpalMCE_Disposition disposition:8; /* 0x05 */
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uint8_t reserved_1[2]; /* 0x06 */
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uint64_t gpr3; /* 0x08 */
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uint64_t srr0; /* 0x10 */
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uint64_t srr1; /* 0x18 */
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union { /* 0x20 */
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struct {
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enum OpalMCE_UeErrorType ue_error_type:8;
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uint8_t effective_address_provided;
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uint8_t physical_address_provided;
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uint8_t reserved_1[5];
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uint64_t effective_address;
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uint64_t physical_address;
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uint8_t reserved_2[8];
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} ue_error;
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struct {
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enum OpalMCE_SlbErrorType slb_error_type:8;
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uint8_t effective_address_provided;
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uint8_t reserved_1[6];
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uint64_t effective_address;
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uint8_t reserved_2[16];
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} slb_error;
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struct {
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enum OpalMCE_EratErrorType erat_error_type:8;
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uint8_t effective_address_provided;
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uint8_t reserved_1[6];
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uint64_t effective_address;
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uint8_t reserved_2[16];
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} erat_error;
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struct {
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enum OpalMCE_TlbErrorType tlb_error_type:8;
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uint8_t effective_address_provided;
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uint8_t reserved_1[6];
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uint64_t effective_address;
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uint8_t reserved_2[16];
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} tlb_error;
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} u;
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};
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typedef struct oppanel_line {
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/* XXX */
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} oppanel_line_t;
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/* API functions */
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int64_t opal_console_write(int64_t term_number, int64_t *length,
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const uint8_t *buffer);
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int64_t opal_console_read(int64_t term_number, int64_t *length,
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uint8_t *buffer);
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int64_t opal_console_write_buffer_space(int64_t term_number,
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int64_t *length);
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int64_t opal_rtc_read(uint32_t *year_month_day,
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uint64_t *hour_minute_second_millisecond);
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int64_t opal_rtc_write(uint32_t year_month_day,
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uint64_t hour_minute_second_millisecond);
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int64_t opal_cec_power_down(uint64_t request);
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int64_t opal_cec_reboot(void);
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int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
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int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
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int64_t opal_handle_interrupt(uint64_t isn, uint64_t *outstanding_event_mask);
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int64_t opal_poll_events(uint64_t *outstanding_event_mask);
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int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
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uint64_t tce_mem_size);
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int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
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uint64_t tce_mem_size);
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int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint8_t *data);
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int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint16_t *data);
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int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint32_t *data);
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int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint8_t data);
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int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint16_t data);
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int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint32_t data);
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int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
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int64_t opal_get_xive(uint32_t isn, uint16_t *server, uint8_t *priority);
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int64_t opal_register_exception_handler(uint64_t opal_exception,
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uint64_t handler_address,
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uint64_t glue_cache_line);
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int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
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uint8_t *freeze_state,
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uint16_t *pci_error_type,
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uint64_t *phb_status);
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int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
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uint64_t eeh_action_token);
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int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
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int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
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uint16_t window_num, uint16_t enable);
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int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
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uint16_t window_num,
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uint64_t starting_real_address,
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uint64_t starting_pci_address,
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uint16_t segment_size);
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int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
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uint16_t window_type, uint16_t window_num,
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uint16_t segment_num);
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int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
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uint64_t ivt_addr, uint64_t ivt_len,
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uint64_t reject_array_addr,
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uint64_t peltv_addr);
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int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
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uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
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uint8_t pe_action);
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int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
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uint8_t state);
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int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
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int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
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uint32_t state);
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int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
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uint8_t *p_bit, uint8_t *q_bit);
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int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
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uint8_t p_bit, uint8_t q_bit);
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int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
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uint32_t xive_num);
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int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
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int32_t *interrupt_source_number);
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int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
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uint8_t msi_range, uint32_t *msi_address,
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uint32_t *message_data);
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int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
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uint32_t xive_num, uint8_t msi_range,
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uint64_t *msi_address, uint32_t *message_data);
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int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
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int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
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int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
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int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
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uint16_t tce_levels, uint64_t tce_table_addr,
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uint64_t tce_table_size, uint64_t tce_page_size);
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int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
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uint16_t dma_window_number, uint64_t pci_start_addr,
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uint64_t pci_mem_size);
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int64_t opal_pci_reset(uint64_t phb_id, uint8_t reset_scope, uint8_t assert_state);
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/* Internal functions */
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extern int early_init_dt_scan_opal(unsigned long node, const char *uname, int depth, void *data);
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extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
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extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
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extern void hvc_opal_init_early(void);
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/* Internal functions */
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extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
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int depth, void *data);
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extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
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extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
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extern void hvc_opal_init_early(void);
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struct rtc_time;
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extern int opal_set_rtc_time(struct rtc_time *tm);
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extern void opal_get_rtc_time(struct rtc_time *tm);
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extern unsigned long opal_get_boot_time(void);
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extern void opal_nvram_init(void);
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#endif /* __ASSEMBLY__ */
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#endif /* __OPAL_H */
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