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The powered-down state of Tegra20 requires power gating both CPU cores. When the secondary CPU requests to enter powered-down state, it saves its own contexts and then enters WFI. The Tegra20 had a limition to power down both CPU cores. The secondary CPU must waits for CPU0 in powered-down state too. If the secondary CPU be woken up before CPU0 entering powered-down state, then it needs to restore its CPU states and waits for next chance. Be aware of that, you may see the legacy power state "LP2" in the code which is exactly the same meaning of "CPU power down". Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
220 lines
4.8 KiB
C
220 lines
4.8 KiB
C
/*
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* CPU complex suspend & resume functions for Tegra SoCs
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*
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* Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/cpu_pm.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/clk/tegra.h>
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#include <asm/smp_plat.h>
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#include <asm/cacheflush.h>
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#include <asm/suspend.h>
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#include <asm/idmap.h>
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#include <asm/proc-fns.h>
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#include <asm/tlbflush.h>
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#include "iomap.h"
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#include "reset.h"
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#include "flowctrl.h"
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#include "fuse.h"
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#include "sleep.h"
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#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
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#define PMC_CTRL 0x0
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#define PMC_CPUPWRGOOD_TIMER 0xc8
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#define PMC_CPUPWROFF_TIMER 0xcc
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#ifdef CONFIG_PM_SLEEP
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static unsigned int g_diag_reg;
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static DEFINE_SPINLOCK(tegra_lp2_lock);
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static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
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static struct clk *tegra_pclk;
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void (*tegra_tear_down_cpu)(void);
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void save_cpu_arch_register(void)
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{
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/* read diagnostic register */
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asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
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return;
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}
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void restore_cpu_arch_register(void)
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{
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/* write diagnostic register */
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asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
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return;
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}
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static void set_power_timers(unsigned long us_on, unsigned long us_off)
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{
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unsigned long long ticks;
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unsigned long long pclk;
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unsigned long rate;
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static unsigned long tegra_last_pclk;
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if (tegra_pclk == NULL) {
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tegra_pclk = clk_get_sys(NULL, "pclk");
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WARN_ON(IS_ERR(tegra_pclk));
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}
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rate = clk_get_rate(tegra_pclk);
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if (WARN_ON_ONCE(rate <= 0))
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pclk = 100000000;
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else
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pclk = rate;
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if ((rate != tegra_last_pclk)) {
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ticks = (us_on * pclk) + 999999ull;
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do_div(ticks, 1000000);
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writel((unsigned long)ticks, pmc + PMC_CPUPWRGOOD_TIMER);
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ticks = (us_off * pclk) + 999999ull;
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do_div(ticks, 1000000);
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writel((unsigned long)ticks, pmc + PMC_CPUPWROFF_TIMER);
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wmb();
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}
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tegra_last_pclk = pclk;
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}
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/*
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* restore_cpu_complex
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*
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* restores cpu clock setting, clears flow controller
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*
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* Always called on CPU 0.
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*/
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static void restore_cpu_complex(void)
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{
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int cpu = smp_processor_id();
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BUG_ON(cpu != 0);
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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/* Restore the CPU clock settings */
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tegra_cpu_clock_resume();
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flowctrl_cpu_suspend_exit(cpu);
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restore_cpu_arch_register();
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}
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/*
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* suspend_cpu_complex
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*
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* saves pll state for use by restart_plls, prepares flow controller for
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* transition to suspend state
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*
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* Must always be called on cpu 0.
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*/
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static void suspend_cpu_complex(void)
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{
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int cpu = smp_processor_id();
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BUG_ON(cpu != 0);
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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/* Save the CPU clock settings */
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tegra_cpu_clock_suspend();
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flowctrl_cpu_suspend_enter(cpu);
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save_cpu_arch_register();
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}
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void tegra_clear_cpu_in_lp2(int phy_cpu_id)
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{
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u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
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spin_lock(&tegra_lp2_lock);
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BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
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*cpu_in_lp2 &= ~BIT(phy_cpu_id);
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spin_unlock(&tegra_lp2_lock);
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}
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bool tegra_set_cpu_in_lp2(int phy_cpu_id)
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{
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bool last_cpu = false;
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cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
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u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
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spin_lock(&tegra_lp2_lock);
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BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
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*cpu_in_lp2 |= BIT(phy_cpu_id);
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if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
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last_cpu = true;
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else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1)
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tegra20_cpu_set_resettable_soon();
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spin_unlock(&tegra_lp2_lock);
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return last_cpu;
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}
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static int tegra_sleep_cpu(unsigned long v2p)
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{
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/* Switch to the identity mapping. */
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cpu_switch_mm(idmap_pgd, &init_mm);
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/* Flush the TLB. */
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local_flush_tlb_all();
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tegra_sleep_cpu_finish(v2p);
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/* should never here */
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BUG();
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return 0;
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}
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void tegra_idle_lp2_last(u32 cpu_on_time, u32 cpu_off_time)
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{
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u32 mode;
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/* Only the last cpu down does the final suspend steps */
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mode = readl(pmc + PMC_CTRL);
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mode |= TEGRA_POWER_CPU_PWRREQ_OE;
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writel(mode, pmc + PMC_CTRL);
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set_power_timers(cpu_on_time, cpu_off_time);
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cpu_cluster_pm_enter();
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suspend_cpu_complex();
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cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
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restore_cpu_complex();
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cpu_cluster_pm_exit();
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}
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#endif
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