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This patch adds DT bindings for the new Microchip I2S Multi-Channel controller embedded inside sam9x60 SoCs. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
44 lines
1.7 KiB
Plaintext
44 lines
1.7 KiB
Plaintext
* Microchip I2S Multi-Channel Controller
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Required properties:
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- compatible: Should be "microchip,sam9x60-i2smcc".
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- reg: Should be the physical base address of the controller and the
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length of memory mapped region.
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- interrupts: Should contain the interrupt for the controller.
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- dmas: Should be one per channel name listed in the dma-names property,
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as described in atmel-dma.txt and dma.txt files.
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- dma-names: Identifier string for each DMA request line in the dmas property.
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Two dmas have to be defined, "tx" and "rx".
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- clocks: Must contain an entry for each entry in clock-names.
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Please refer to clock-bindings.txt.
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- clock-names: Should be one of each entry matching the clocks phandles list:
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- "pclk" (peripheral clock) Required.
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- "gclk" (generated clock) Optional (1).
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Optional properties:
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- pinctrl-0: Should specify pin control groups used for this controller.
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- princtrl-names: Should contain only one value - "default".
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(1) : Only the peripheral clock is required. The generated clock is optional
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and should be set mostly when Master Mode is required.
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Example:
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i2s@f001c000 {
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compatible = "microchip,sam9x60-i2smcc";
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reg = <0xf001c000 0x100>;
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interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
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dmas = <&dma0
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(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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AT91_XDMAC_DT_PERID(36))>,
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<&dma0
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(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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AT91_XDMAC_DT_PERID(37))>;
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dma-names = "tx", "rx";
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clocks = <&i2s_clk>, <&i2s_gclk>;
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clock-names = "pclk", "gclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2s_default>;
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};
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