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05492f2fd8
The LSE atomics are implemented using alternative code sequences of different lengths, and explicit NOP padding is used to ensure the patching works correctly. This patch converts the bulk of the LSE code over to using the __nops macro, which makes it slightly clearer as to what is going on and also consolidates all of the padding at the end of the various sequences. Signed-off-by: Will Deacon <will.deacon@arm.com>
535 lines
15 KiB
C
535 lines
15 KiB
C
/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ATOMIC_LSE_H
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#define __ASM_ATOMIC_LSE_H
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#ifndef __ARM64_IN_ATOMIC_IMPL
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#error "please don't include this file directly"
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#endif
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#define __LL_SC_ATOMIC(op) __LL_SC_CALL(atomic_##op)
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#define ATOMIC_OP(op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC(op), \
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" " #asm_op " %w[i], %[v]\n") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS); \
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}
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ATOMIC_OP(andnot, stclr)
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ATOMIC_OP(or, stset)
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ATOMIC_OP(xor, steor)
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ATOMIC_OP(add, stadd)
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#undef ATOMIC_OP
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#define ATOMIC_FETCH_OP(name, mb, op, asm_op, cl...) \
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static inline int atomic_fetch_##op##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC(fetch_##op##name), \
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/* LSE atomics */ \
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" " #asm_op #mb " %w[i], %w[i], %[v]") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return w0; \
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}
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#define ATOMIC_FETCH_OPS(op, asm_op) \
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ATOMIC_FETCH_OP(_relaxed, , op, asm_op) \
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ATOMIC_FETCH_OP(_acquire, a, op, asm_op, "memory") \
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ATOMIC_FETCH_OP(_release, l, op, asm_op, "memory") \
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ATOMIC_FETCH_OP( , al, op, asm_op, "memory")
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ATOMIC_FETCH_OPS(andnot, ldclr)
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ATOMIC_FETCH_OPS(or, ldset)
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ATOMIC_FETCH_OPS(xor, ldeor)
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ATOMIC_FETCH_OPS(add, ldadd)
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_FETCH_OPS
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#define ATOMIC_OP_ADD_RETURN(name, mb, cl...) \
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static inline int atomic_add_return##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC(add_return##name) \
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__nops(1), \
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/* LSE atomics */ \
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" ldadd" #mb " %w[i], w30, %[v]\n" \
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" add %w[i], %w[i], w30") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return w0; \
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}
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ATOMIC_OP_ADD_RETURN(_relaxed, )
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ATOMIC_OP_ADD_RETURN(_acquire, a, "memory")
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ATOMIC_OP_ADD_RETURN(_release, l, "memory")
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ATOMIC_OP_ADD_RETURN( , al, "memory")
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#undef ATOMIC_OP_ADD_RETURN
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static inline void atomic_and(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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__LL_SC_ATOMIC(and)
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__nops(1),
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/* LSE atomics */
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" mvn %w[i], %w[i]\n"
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" stclr %w[i], %[v]")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: __LL_SC_CLOBBERS);
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}
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#define ATOMIC_FETCH_OP_AND(name, mb, cl...) \
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static inline int atomic_fetch_and##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC(fetch_and##name) \
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__nops(1), \
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/* LSE atomics */ \
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" mvn %w[i], %w[i]\n" \
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" ldclr" #mb " %w[i], %w[i], %[v]") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return w0; \
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}
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ATOMIC_FETCH_OP_AND(_relaxed, )
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ATOMIC_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC_FETCH_OP_AND(_release, l, "memory")
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ATOMIC_FETCH_OP_AND( , al, "memory")
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#undef ATOMIC_FETCH_OP_AND
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static inline void atomic_sub(int i, atomic_t *v)
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{
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register int w0 asm ("w0") = i;
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register atomic_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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__LL_SC_ATOMIC(sub)
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__nops(1),
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/* LSE atomics */
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" neg %w[i], %w[i]\n"
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" stadd %w[i], %[v]")
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: [i] "+r" (w0), [v] "+Q" (v->counter)
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: "r" (x1)
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: __LL_SC_CLOBBERS);
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}
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#define ATOMIC_OP_SUB_RETURN(name, mb, cl...) \
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static inline int atomic_sub_return##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC(sub_return##name) \
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__nops(2), \
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/* LSE atomics */ \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], w30, %[v]\n" \
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" add %w[i], %w[i], w30") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS , ##cl); \
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\
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return w0; \
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}
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ATOMIC_OP_SUB_RETURN(_relaxed, )
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ATOMIC_OP_SUB_RETURN(_acquire, a, "memory")
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ATOMIC_OP_SUB_RETURN(_release, l, "memory")
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ATOMIC_OP_SUB_RETURN( , al, "memory")
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#undef ATOMIC_OP_SUB_RETURN
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#define ATOMIC_FETCH_OP_SUB(name, mb, cl...) \
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static inline int atomic_fetch_sub##name(int i, atomic_t *v) \
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{ \
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register int w0 asm ("w0") = i; \
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register atomic_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC(fetch_sub##name) \
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__nops(1), \
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/* LSE atomics */ \
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" neg %w[i], %w[i]\n" \
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" ldadd" #mb " %w[i], %w[i], %[v]") \
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: [i] "+r" (w0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return w0; \
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}
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ATOMIC_FETCH_OP_SUB(_relaxed, )
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ATOMIC_FETCH_OP_SUB(_acquire, a, "memory")
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ATOMIC_FETCH_OP_SUB(_release, l, "memory")
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ATOMIC_FETCH_OP_SUB( , al, "memory")
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#undef ATOMIC_FETCH_OP_SUB
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#undef __LL_SC_ATOMIC
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#define __LL_SC_ATOMIC64(op) __LL_SC_CALL(atomic64_##op)
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#define ATOMIC64_OP(op, asm_op) \
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static inline void atomic64_##op(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN(__LL_SC_ATOMIC64(op), \
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" " #asm_op " %[i], %[v]\n") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS); \
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}
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ATOMIC64_OP(andnot, stclr)
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ATOMIC64_OP(or, stset)
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ATOMIC64_OP(xor, steor)
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ATOMIC64_OP(add, stadd)
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#undef ATOMIC64_OP
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#define ATOMIC64_FETCH_OP(name, mb, op, asm_op, cl...) \
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static inline long atomic64_fetch_##op##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC64(fetch_##op##name), \
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/* LSE atomics */ \
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" " #asm_op #mb " %[i], %[i], %[v]") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return x0; \
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}
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#define ATOMIC64_FETCH_OPS(op, asm_op) \
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ATOMIC64_FETCH_OP(_relaxed, , op, asm_op) \
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ATOMIC64_FETCH_OP(_acquire, a, op, asm_op, "memory") \
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ATOMIC64_FETCH_OP(_release, l, op, asm_op, "memory") \
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ATOMIC64_FETCH_OP( , al, op, asm_op, "memory")
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ATOMIC64_FETCH_OPS(andnot, ldclr)
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ATOMIC64_FETCH_OPS(or, ldset)
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ATOMIC64_FETCH_OPS(xor, ldeor)
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ATOMIC64_FETCH_OPS(add, ldadd)
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_FETCH_OPS
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#define ATOMIC64_OP_ADD_RETURN(name, mb, cl...) \
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static inline long atomic64_add_return##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC64(add_return##name) \
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__nops(1), \
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/* LSE atomics */ \
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" ldadd" #mb " %[i], x30, %[v]\n" \
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" add %[i], %[i], x30") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return x0; \
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}
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ATOMIC64_OP_ADD_RETURN(_relaxed, )
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ATOMIC64_OP_ADD_RETURN(_acquire, a, "memory")
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ATOMIC64_OP_ADD_RETURN(_release, l, "memory")
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ATOMIC64_OP_ADD_RETURN( , al, "memory")
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#undef ATOMIC64_OP_ADD_RETURN
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static inline void atomic64_and(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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__LL_SC_ATOMIC64(and)
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__nops(1),
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/* LSE atomics */
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" mvn %[i], %[i]\n"
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" stclr %[i], %[v]")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: __LL_SC_CLOBBERS);
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}
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#define ATOMIC64_FETCH_OP_AND(name, mb, cl...) \
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static inline long atomic64_fetch_and##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("w0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC64(fetch_and##name) \
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__nops(1), \
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/* LSE atomics */ \
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" mvn %[i], %[i]\n" \
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" ldclr" #mb " %[i], %[i], %[v]") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return x0; \
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}
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ATOMIC64_FETCH_OP_AND(_relaxed, )
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ATOMIC64_FETCH_OP_AND(_acquire, a, "memory")
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ATOMIC64_FETCH_OP_AND(_release, l, "memory")
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ATOMIC64_FETCH_OP_AND( , al, "memory")
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#undef ATOMIC64_FETCH_OP_AND
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static inline void atomic64_sub(long i, atomic64_t *v)
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{
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register long x0 asm ("x0") = i;
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register atomic64_t *x1 asm ("x1") = v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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__LL_SC_ATOMIC64(sub)
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__nops(1),
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/* LSE atomics */
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" neg %[i], %[i]\n"
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" stadd %[i], %[v]")
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: [i] "+r" (x0), [v] "+Q" (v->counter)
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: "r" (x1)
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: __LL_SC_CLOBBERS);
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}
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#define ATOMIC64_OP_SUB_RETURN(name, mb, cl...) \
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static inline long atomic64_sub_return##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("x0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC64(sub_return##name) \
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__nops(2), \
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/* LSE atomics */ \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], x30, %[v]\n" \
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" add %[i], %[i], x30") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return x0; \
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}
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ATOMIC64_OP_SUB_RETURN(_relaxed, )
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ATOMIC64_OP_SUB_RETURN(_acquire, a, "memory")
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ATOMIC64_OP_SUB_RETURN(_release, l, "memory")
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ATOMIC64_OP_SUB_RETURN( , al, "memory")
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#undef ATOMIC64_OP_SUB_RETURN
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#define ATOMIC64_FETCH_OP_SUB(name, mb, cl...) \
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static inline long atomic64_fetch_sub##name(long i, atomic64_t *v) \
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{ \
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register long x0 asm ("w0") = i; \
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register atomic64_t *x1 asm ("x1") = v; \
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\
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asm volatile(ARM64_LSE_ATOMIC_INSN( \
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/* LL/SC */ \
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__LL_SC_ATOMIC64(fetch_sub##name) \
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__nops(1), \
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/* LSE atomics */ \
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" neg %[i], %[i]\n" \
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" ldadd" #mb " %[i], %[i], %[v]") \
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: [i] "+r" (x0), [v] "+Q" (v->counter) \
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: "r" (x1) \
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: __LL_SC_CLOBBERS, ##cl); \
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\
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return x0; \
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}
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ATOMIC64_FETCH_OP_SUB(_relaxed, )
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ATOMIC64_FETCH_OP_SUB(_acquire, a, "memory")
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ATOMIC64_FETCH_OP_SUB(_release, l, "memory")
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ATOMIC64_FETCH_OP_SUB( , al, "memory")
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#undef ATOMIC64_FETCH_OP_SUB
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static inline long atomic64_dec_if_positive(atomic64_t *v)
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{
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register long x0 asm ("x0") = (long)v;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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__LL_SC_ATOMIC64(dec_if_positive)
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__nops(6),
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/* LSE atomics */
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"1: ldr x30, %[v]\n"
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" subs %[ret], x30, #1\n"
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" b.lt 2f\n"
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" casal x30, %[ret], %[v]\n"
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" sub x30, x30, #1\n"
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" sub x30, x30, %[ret]\n"
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" cbnz x30, 1b\n"
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"2:")
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: [ret] "+&r" (x0), [v] "+Q" (v->counter)
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:
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: __LL_SC_CLOBBERS, "cc", "memory");
|
|
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return x0;
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}
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|
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#undef __LL_SC_ATOMIC64
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|
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|
#define __LL_SC_CMPXCHG(op) __LL_SC_CALL(__cmpxchg_case_##op)
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|
|
|
#define __CMPXCHG_CASE(w, sz, name, mb, cl...) \
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static inline unsigned long __cmpxchg_case_##name(volatile void *ptr, \
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unsigned long old, \
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|
unsigned long new) \
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|
{ \
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register unsigned long x0 asm ("x0") = (unsigned long)ptr; \
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register unsigned long x1 asm ("x1") = old; \
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register unsigned long x2 asm ("x2") = new; \
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|
\
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|
asm volatile(ARM64_LSE_ATOMIC_INSN( \
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|
/* LL/SC */ \
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|
__LL_SC_CMPXCHG(name) \
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|
__nops(2), \
|
|
/* LSE atomics */ \
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|
" mov " #w "30, %" #w "[old]\n" \
|
|
" cas" #mb #sz "\t" #w "30, %" #w "[new], %[v]\n" \
|
|
" mov %" #w "[ret], " #w "30") \
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|
: [ret] "+r" (x0), [v] "+Q" (*(unsigned long *)ptr) \
|
|
: [old] "r" (x1), [new] "r" (x2) \
|
|
: __LL_SC_CLOBBERS, ##cl); \
|
|
\
|
|
return x0; \
|
|
}
|
|
|
|
__CMPXCHG_CASE(w, b, 1, )
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|
__CMPXCHG_CASE(w, h, 2, )
|
|
__CMPXCHG_CASE(w, , 4, )
|
|
__CMPXCHG_CASE(x, , 8, )
|
|
__CMPXCHG_CASE(w, b, acq_1, a, "memory")
|
|
__CMPXCHG_CASE(w, h, acq_2, a, "memory")
|
|
__CMPXCHG_CASE(w, , acq_4, a, "memory")
|
|
__CMPXCHG_CASE(x, , acq_8, a, "memory")
|
|
__CMPXCHG_CASE(w, b, rel_1, l, "memory")
|
|
__CMPXCHG_CASE(w, h, rel_2, l, "memory")
|
|
__CMPXCHG_CASE(w, , rel_4, l, "memory")
|
|
__CMPXCHG_CASE(x, , rel_8, l, "memory")
|
|
__CMPXCHG_CASE(w, b, mb_1, al, "memory")
|
|
__CMPXCHG_CASE(w, h, mb_2, al, "memory")
|
|
__CMPXCHG_CASE(w, , mb_4, al, "memory")
|
|
__CMPXCHG_CASE(x, , mb_8, al, "memory")
|
|
|
|
#undef __LL_SC_CMPXCHG
|
|
#undef __CMPXCHG_CASE
|
|
|
|
#define __LL_SC_CMPXCHG_DBL(op) __LL_SC_CALL(__cmpxchg_double##op)
|
|
|
|
#define __CMPXCHG_DBL(name, mb, cl...) \
|
|
static inline long __cmpxchg_double##name(unsigned long old1, \
|
|
unsigned long old2, \
|
|
unsigned long new1, \
|
|
unsigned long new2, \
|
|
volatile void *ptr) \
|
|
{ \
|
|
unsigned long oldval1 = old1; \
|
|
unsigned long oldval2 = old2; \
|
|
register unsigned long x0 asm ("x0") = old1; \
|
|
register unsigned long x1 asm ("x1") = old2; \
|
|
register unsigned long x2 asm ("x2") = new1; \
|
|
register unsigned long x3 asm ("x3") = new2; \
|
|
register unsigned long x4 asm ("x4") = (unsigned long)ptr; \
|
|
\
|
|
asm volatile(ARM64_LSE_ATOMIC_INSN( \
|
|
/* LL/SC */ \
|
|
__LL_SC_CMPXCHG_DBL(name) \
|
|
__nops(3), \
|
|
/* LSE atomics */ \
|
|
" casp" #mb "\t%[old1], %[old2], %[new1], %[new2], %[v]\n"\
|
|
" eor %[old1], %[old1], %[oldval1]\n" \
|
|
" eor %[old2], %[old2], %[oldval2]\n" \
|
|
" orr %[old1], %[old1], %[old2]") \
|
|
: [old1] "+r" (x0), [old2] "+r" (x1), \
|
|
[v] "+Q" (*(unsigned long *)ptr) \
|
|
: [new1] "r" (x2), [new2] "r" (x3), [ptr] "r" (x4), \
|
|
[oldval1] "r" (oldval1), [oldval2] "r" (oldval2) \
|
|
: __LL_SC_CLOBBERS, ##cl); \
|
|
\
|
|
return x0; \
|
|
}
|
|
|
|
__CMPXCHG_DBL( , )
|
|
__CMPXCHG_DBL(_mb, al, "memory")
|
|
|
|
#undef __LL_SC_CMPXCHG_DBL
|
|
#undef __CMPXCHG_DBL
|
|
|
|
#endif /* __ASM_ATOMIC_LSE_H */
|