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Erratum A-008585 says that the ARM generic timer counter "has the potential to contain an erroneous value for a small number of core clock cycles every time the timer value changes". Accesses to TVAL (both read and write) are also affected due to the implicit counter read. Accesses to CVAL are not affected. The workaround is to reread TVAL and count registers until successive reads return the same value. Writes to TVAL are replaced with an equivalent write to CVAL. The workaround is to reread TVAL and count registers until successive reads return the same value, and when writing TVAL to retry until counter reads before and after the write return the same value. The workaround is enabled if the fsl,erratum-a008585 property is found in the timer node in the device tree. This can be overridden with the clocksource.arm_arch_timer.fsl-a008585 boot parameter, which allows KVM users to enable the workaround until a mechanism is implemented to automatically communicate this information. This erratum can be found on LS1043A and LS2080A. Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Scott Wood <oss@buserror.net> [will: renamed read macro to reflect that it's not usually unstable] Signed-off-by: Will Deacon <will.deacon@arm.com>
161 lines
3.7 KiB
C
161 lines
3.7 KiB
C
/*
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* arch/arm64/include/asm/arch_timer.h
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*
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* Copyright (C) 2012 ARM Ltd.
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ARCH_TIMER_H
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#define __ASM_ARCH_TIMER_H
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#include <asm/barrier.h>
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#include <asm/sysreg.h>
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#include <linux/bug.h>
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#include <linux/init.h>
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#include <linux/jump_label.h>
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#include <linux/types.h>
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#include <clocksource/arm_arch_timer.h>
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#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
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extern struct static_key_false arch_timer_read_ool_enabled;
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#define needs_fsl_a008585_workaround() \
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static_branch_unlikely(&arch_timer_read_ool_enabled)
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#else
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#define needs_fsl_a008585_workaround() false
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#endif
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u32 __fsl_a008585_read_cntp_tval_el0(void);
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u32 __fsl_a008585_read_cntv_tval_el0(void);
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u64 __fsl_a008585_read_cntvct_el0(void);
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/*
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* The number of retries is an arbitrary value well beyond the highest number
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* of iterations the loop has been observed to take.
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*/
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#define __fsl_a008585_read_reg(reg) ({ \
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u64 _old, _new; \
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int _retries = 200; \
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\
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do { \
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_old = read_sysreg(reg); \
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_new = read_sysreg(reg); \
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_retries--; \
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} while (unlikely(_old != _new) && _retries); \
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\
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WARN_ON_ONCE(!_retries); \
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_new; \
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})
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#define arch_timer_reg_read_stable(reg) \
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({ \
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u64 _val; \
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if (needs_fsl_a008585_workaround()) \
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_val = __fsl_a008585_read_##reg(); \
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else \
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_val = read_sysreg(reg); \
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_val; \
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})
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/*
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* These register accessors are marked inline so the compiler can
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* nicely work out which register we want, and chuck away the rest of
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* the code.
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*/
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static __always_inline
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void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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write_sysreg(val, cntp_ctl_el0);
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break;
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case ARCH_TIMER_REG_TVAL:
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write_sysreg(val, cntp_tval_el0);
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break;
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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write_sysreg(val, cntv_ctl_el0);
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break;
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case ARCH_TIMER_REG_TVAL:
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write_sysreg(val, cntv_tval_el0);
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break;
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}
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}
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isb();
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}
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static __always_inline
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u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
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{
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if (access == ARCH_TIMER_PHYS_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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return read_sysreg(cntp_ctl_el0);
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case ARCH_TIMER_REG_TVAL:
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return arch_timer_reg_read_stable(cntp_tval_el0);
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}
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} else if (access == ARCH_TIMER_VIRT_ACCESS) {
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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return read_sysreg(cntv_ctl_el0);
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case ARCH_TIMER_REG_TVAL:
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return arch_timer_reg_read_stable(cntv_tval_el0);
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}
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}
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BUG();
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}
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static inline u32 arch_timer_get_cntfrq(void)
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{
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return read_sysreg(cntfrq_el0);
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}
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static inline u32 arch_timer_get_cntkctl(void)
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{
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return read_sysreg(cntkctl_el1);
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}
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static inline void arch_timer_set_cntkctl(u32 cntkctl)
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{
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write_sysreg(cntkctl, cntkctl_el1);
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}
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static inline u64 arch_counter_get_cntpct(void)
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{
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/*
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* AArch64 kernel and user space mandate the use of CNTVCT.
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*/
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BUG();
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return 0;
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}
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static inline u64 arch_counter_get_cntvct(void)
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{
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isb();
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return arch_timer_reg_read_stable(cntvct_el0);
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}
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static inline int arch_timer_arch_init(void)
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{
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return 0;
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}
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#endif
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