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61c951dedc
SDHCI provides more flexibility than simply calling sdhci_add_host(). Make that available by allowing devices to specify their own ->add_host() function. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Ludovic Desroches <ludovic.desroches@microchip.com>
113 lines
2.9 KiB
C
113 lines
2.9 KiB
C
#ifndef __SDHCI_PCI_H
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#define __SDHCI_PCI_H
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/*
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* PCI device IDs
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*/
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#define PCI_DEVICE_ID_INTEL_PCH_SDIO0 0x8809
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#define PCI_DEVICE_ID_INTEL_PCH_SDIO1 0x880a
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#define PCI_DEVICE_ID_INTEL_BYT_EMMC 0x0f14
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#define PCI_DEVICE_ID_INTEL_BYT_SDIO 0x0f15
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#define PCI_DEVICE_ID_INTEL_BYT_SD 0x0f16
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#define PCI_DEVICE_ID_INTEL_BYT_EMMC2 0x0f50
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#define PCI_DEVICE_ID_INTEL_BSW_EMMC 0x2294
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#define PCI_DEVICE_ID_INTEL_BSW_SDIO 0x2295
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#define PCI_DEVICE_ID_INTEL_BSW_SD 0x2296
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#define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO0 0x08f9
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO1 0x08fa
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#define PCI_DEVICE_ID_INTEL_CLV_SDIO2 0x08fb
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#define PCI_DEVICE_ID_INTEL_CLV_EMMC0 0x08e5
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#define PCI_DEVICE_ID_INTEL_CLV_EMMC1 0x08e6
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#define PCI_DEVICE_ID_INTEL_QRK_SD 0x08A7
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#define PCI_DEVICE_ID_INTEL_SPT_EMMC 0x9d2b
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#define PCI_DEVICE_ID_INTEL_SPT_SDIO 0x9d2c
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#define PCI_DEVICE_ID_INTEL_SPT_SD 0x9d2d
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#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
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#define PCI_DEVICE_ID_INTEL_BXT_SD 0x0aca
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#define PCI_DEVICE_ID_INTEL_BXT_EMMC 0x0acc
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#define PCI_DEVICE_ID_INTEL_BXT_SDIO 0x0ad0
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#define PCI_DEVICE_ID_INTEL_BXTM_SD 0x1aca
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#define PCI_DEVICE_ID_INTEL_BXTM_EMMC 0x1acc
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#define PCI_DEVICE_ID_INTEL_BXTM_SDIO 0x1ad0
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#define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca
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#define PCI_DEVICE_ID_INTEL_APL_EMMC 0x5acc
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#define PCI_DEVICE_ID_INTEL_APL_SDIO 0x5ad0
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#define PCI_DEVICE_ID_INTEL_GLK_SD 0x31ca
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#define PCI_DEVICE_ID_INTEL_GLK_EMMC 0x31cc
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#define PCI_DEVICE_ID_INTEL_GLK_SDIO 0x31d0
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/*
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* PCI registers
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*/
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#define PCI_SDHCI_IFPIO 0x00
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#define PCI_SDHCI_IFDMA 0x01
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#define PCI_SDHCI_IFVENDOR 0x02
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#define PCI_SLOT_INFO 0x40 /* 8 bits */
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#define PCI_SLOT_INFO_SLOTS(x) ((x >> 4) & 7)
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#define PCI_SLOT_INFO_FIRST_BAR_MASK 0x07
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#define MAX_SLOTS 8
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struct sdhci_pci_chip;
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struct sdhci_pci_slot;
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struct sdhci_pci_fixes {
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unsigned int quirks;
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unsigned int quirks2;
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bool allow_runtime_pm;
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bool own_cd_for_runtime_pm;
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int (*probe) (struct sdhci_pci_chip *);
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int (*probe_slot) (struct sdhci_pci_slot *);
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int (*add_host) (struct sdhci_pci_slot *);
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void (*remove_slot) (struct sdhci_pci_slot *, int);
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int (*suspend) (struct sdhci_pci_chip *);
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int (*resume) (struct sdhci_pci_chip *);
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const struct sdhci_ops *ops;
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size_t priv_size;
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};
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struct sdhci_pci_slot {
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struct sdhci_pci_chip *chip;
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struct sdhci_host *host;
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struct sdhci_pci_data *data;
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int rst_n_gpio;
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int cd_gpio;
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int cd_irq;
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int cd_idx;
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bool cd_override_level;
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void (*hw_reset)(struct sdhci_host *host);
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unsigned long private[0] ____cacheline_aligned;
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};
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struct sdhci_pci_chip {
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struct pci_dev *pdev;
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unsigned int quirks;
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unsigned int quirks2;
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bool allow_runtime_pm;
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bool pm_retune;
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bool rpm_retune;
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const struct sdhci_pci_fixes *fixes;
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int num_slots; /* Slots on controller */
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struct sdhci_pci_slot *slots[MAX_SLOTS]; /* Pointers to host slots */
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};
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static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
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{
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return (void *)slot->private;
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}
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#endif /* __SDHCI_PCI_H */
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