mirror of
https://github.com/torvalds/linux.git
synced 2024-12-26 21:02:19 +00:00
ea1fe3a887
This is due to duplicated unistd inclusion (via uClibc headers + kernel headers)
Also seen on ARM uClibc based tools
------- ARC build ---------->8-------------
CC util/evlist.o
In file included from
~/arc/k.org/arch/arc/include/uapi/asm/unistd.h:25:0,
from util/../perf-sys.h:10,
from util/../perf.h:15,
from util/event.h:7,
from util/event.c:3:
~/arc/k.org/include/uapi/asm-generic/unistd.h:906:0:
warning: "__NR_fcntl64" redefined [enabled by default]
#define __NR_fcntl64 __NR3264_fcntl
^
In file included from
~/arc/gnu/INSTALL_1412-arc-2014.12-rc1/arc-snps-linux-uclibc/sysroot/usr/include/sys/syscall.h:24:0,
from util/../perf-sys.h:6,
----------------->8-------------------
------- ARM build ---------->8-------------
CC FPIC plugin_scsi.o
In file included from util/../perf-sys.h:9:0,
from util/../perf.h:15,
from util/cache.h:7,
from perf.c:12:
~/arc/k.org/arch/arm/include/uapi/asm/unistd.h:28:0:
warning: "__NR_restart_syscall" redefined [enabled by default]
In file included from
~/buildroot/host/usr/arm-buildroot-linux-uclibcgnueabi/sysroot/usr/include/sys/syscall.h:25:0,
from util/../perf-sys.h:6,
from util/../perf.h:15,
from util/cache.h:7,
from perf.c:12:
~/buildroot/host/usr/arm-buildroot-linux-uclibcgnueabi/sysroot/usr/include/bits/sysnum.h:17:0:
note: this is the location of the previous definition
----------------->8-------------------
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Alexey Brodkin <Alexey.Brodkin@synopsys.com>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1421156604-30603-4-git-send-email-vgupta@synopsys.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
191 lines
5.0 KiB
C
191 lines
5.0 KiB
C
#ifndef _PERF_SYS_H
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#define _PERF_SYS_H
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#include <unistd.h>
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#include <sys/types.h>
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#include <sys/syscall.h>
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#include <linux/types.h>
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#include <linux/perf_event.h>
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#if defined(__i386__)
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#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#define CPUINFO_PROC {"model name"}
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#ifndef __NR_perf_event_open
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# define __NR_perf_event_open 336
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#endif
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#ifndef __NR_futex
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# define __NR_futex 240
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#endif
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#ifndef __NR_gettid
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# define __NR_gettid 224
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#endif
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#endif
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#if defined(__x86_64__)
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#define mb() asm volatile("mfence" ::: "memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#define rmb() asm volatile("lfence" ::: "memory")
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#define cpu_relax() asm volatile("rep; nop" ::: "memory");
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#define CPUINFO_PROC {"model name"}
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#ifndef __NR_perf_event_open
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# define __NR_perf_event_open 298
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#endif
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#ifndef __NR_futex
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# define __NR_futex 202
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#endif
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#ifndef __NR_gettid
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# define __NR_gettid 186
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#endif
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#endif
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#ifdef __powerpc__
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#include "../../arch/powerpc/include/uapi/asm/unistd.h"
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#define mb() asm volatile ("sync" ::: "memory")
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#define wmb() asm volatile ("sync" ::: "memory")
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#define rmb() asm volatile ("sync" ::: "memory")
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#define CPUINFO_PROC {"cpu"}
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#endif
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#ifdef __s390__
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#define mb() asm volatile("bcr 15,0" ::: "memory")
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#define wmb() asm volatile("bcr 15,0" ::: "memory")
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#define rmb() asm volatile("bcr 15,0" ::: "memory")
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#define CPUINFO_PROC {"vendor_id"}
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#endif
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#ifdef __sh__
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#if defined(__SH4A__) || defined(__SH5__)
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# define mb() asm volatile("synco" ::: "memory")
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# define wmb() asm volatile("synco" ::: "memory")
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# define rmb() asm volatile("synco" ::: "memory")
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#else
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# define mb() asm volatile("" ::: "memory")
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# define wmb() asm volatile("" ::: "memory")
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# define rmb() asm volatile("" ::: "memory")
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#endif
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#define CPUINFO_PROC {"cpu type"}
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#endif
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#ifdef __hppa__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define CPUINFO_PROC {"cpu"}
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#endif
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#ifdef __sparc__
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#ifdef __LP64__
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#define mb() asm volatile("ba,pt %%xcc, 1f\n" \
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"membar #StoreLoad\n" \
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"1:\n":::"memory")
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#else
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#define mb() asm volatile("":::"memory")
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#endif
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#define wmb() asm volatile("":::"memory")
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#define rmb() asm volatile("":::"memory")
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#define CPUINFO_PROC {"cpu"}
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#endif
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#ifdef __alpha__
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#define mb() asm volatile("mb" ::: "memory")
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#define wmb() asm volatile("wmb" ::: "memory")
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#define rmb() asm volatile("mb" ::: "memory")
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#define CPUINFO_PROC {"cpu model"}
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#endif
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#ifdef __ia64__
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#define mb() asm volatile ("mf" ::: "memory")
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#define wmb() asm volatile ("mf" ::: "memory")
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#define rmb() asm volatile ("mf" ::: "memory")
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#define cpu_relax() asm volatile ("hint @pause" ::: "memory")
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#define CPUINFO_PROC {"model name"}
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#endif
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#ifdef __arm__
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/*
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* Use the __kuser_memory_barrier helper in the CPU helper page. See
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* arch/arm/kernel/entry-armv.S in the kernel source for details.
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*/
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#define mb() ((void(*)(void))0xffff0fa0)()
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#define wmb() ((void(*)(void))0xffff0fa0)()
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#define rmb() ((void(*)(void))0xffff0fa0)()
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#define CPUINFO_PROC {"model name", "Processor"}
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#endif
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#ifdef __aarch64__
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#define mb() asm volatile("dmb ish" ::: "memory")
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#define wmb() asm volatile("dmb ishst" ::: "memory")
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#define rmb() asm volatile("dmb ishld" ::: "memory")
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#define cpu_relax() asm volatile("yield" ::: "memory")
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#endif
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#ifdef __mips__
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#define mb() asm volatile( \
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".set mips2\n\t" \
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"sync\n\t" \
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".set mips0" \
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: /* no output */ \
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: /* no input */ \
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: "memory")
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#define wmb() mb()
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#define rmb() mb()
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#define CPUINFO_PROC {"cpu model"}
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#endif
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#ifdef __arc__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define CPUINFO_PROC {"Processor"}
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#endif
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#ifdef __metag__
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#define mb() asm volatile("" ::: "memory")
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#define wmb() asm volatile("" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define CPUINFO_PROC {"CPU"}
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#endif
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#ifdef __xtensa__
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#define mb() asm volatile("memw" ::: "memory")
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#define wmb() asm volatile("memw" ::: "memory")
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#define rmb() asm volatile("" ::: "memory")
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#define CPUINFO_PROC {"core ID"}
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#endif
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#ifdef __tile__
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#define mb() asm volatile ("mf" ::: "memory")
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#define wmb() asm volatile ("mf" ::: "memory")
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#define rmb() asm volatile ("mf" ::: "memory")
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#define cpu_relax() asm volatile ("mfspr zero, PASS" ::: "memory")
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#define CPUINFO_PROC {"model name"}
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#endif
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#define barrier() asm volatile ("" ::: "memory")
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#ifndef cpu_relax
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#define cpu_relax() barrier()
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#endif
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static inline int
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sys_perf_event_open(struct perf_event_attr *attr,
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pid_t pid, int cpu, int group_fd,
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unsigned long flags)
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{
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int fd;
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fd = syscall(__NR_perf_event_open, attr, pid, cpu,
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group_fd, flags);
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#ifdef HAVE_ATTR_TEST
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if (unlikely(test_attr__enabled))
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test_attr__open(attr, pid, cpu, fd, group_fd, flags);
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#endif
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return fd;
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}
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#endif /* _PERF_SYS_H */
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