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dc6ae2057c
This platform from Ralink was acquired by MediaTek in 2011. Then, MediaTek introduced new SoCs which utilise this platform. Move the driver to mediatek pinctrl directory. Rename the ralink core driver to mtmips. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> Link: https://lore.kernel.org/r/20230317213011.13656-5-arinc.unal@arinc9.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
138 lines
4.9 KiB
C
138 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include "pinctrl-mtmips.h"
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#define MT7620_GPIO_MODE_UART0_SHIFT 2
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#define MT7620_GPIO_MODE_UART0_MASK 0x7
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#define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
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#define MT7620_GPIO_MODE_UARTF 0x0
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#define MT7620_GPIO_MODE_PCM_UARTF 0x1
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#define MT7620_GPIO_MODE_PCM_I2S 0x2
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#define MT7620_GPIO_MODE_I2S_UARTF 0x3
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#define MT7620_GPIO_MODE_PCM_GPIO 0x4
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#define MT7620_GPIO_MODE_GPIO_UARTF 0x5
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#define MT7620_GPIO_MODE_GPIO_I2S 0x6
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#define MT7620_GPIO_MODE_GPIO 0x7
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#define MT7620_GPIO_MODE_NAND 0
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#define MT7620_GPIO_MODE_SD 1
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#define MT7620_GPIO_MODE_ND_SD_GPIO 2
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#define MT7620_GPIO_MODE_ND_SD_MASK 0x3
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#define MT7620_GPIO_MODE_ND_SD_SHIFT 18
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#define MT7620_GPIO_MODE_PCIE_RST 0
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#define MT7620_GPIO_MODE_PCIE_REF 1
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#define MT7620_GPIO_MODE_PCIE_GPIO 2
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#define MT7620_GPIO_MODE_PCIE_MASK 0x3
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#define MT7620_GPIO_MODE_PCIE_SHIFT 16
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#define MT7620_GPIO_MODE_WDT_RST 0
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#define MT7620_GPIO_MODE_WDT_REF 1
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#define MT7620_GPIO_MODE_WDT_GPIO 2
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#define MT7620_GPIO_MODE_WDT_MASK 0x3
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#define MT7620_GPIO_MODE_WDT_SHIFT 21
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#define MT7620_GPIO_MODE_MDIO 0
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#define MT7620_GPIO_MODE_MDIO_REFCLK 1
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#define MT7620_GPIO_MODE_MDIO_GPIO 2
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#define MT7620_GPIO_MODE_MDIO_MASK 0x3
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#define MT7620_GPIO_MODE_MDIO_SHIFT 7
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#define MT7620_GPIO_MODE_I2C 0
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#define MT7620_GPIO_MODE_UART1 5
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#define MT7620_GPIO_MODE_RGMII1 9
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#define MT7620_GPIO_MODE_RGMII2 10
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#define MT7620_GPIO_MODE_SPI 11
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#define MT7620_GPIO_MODE_SPI_REF_CLK 12
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#define MT7620_GPIO_MODE_WLED 13
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#define MT7620_GPIO_MODE_JTAG 15
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#define MT7620_GPIO_MODE_EPHY 15
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#define MT7620_GPIO_MODE_PA 20
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static struct mtmips_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
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static struct mtmips_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
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static struct mtmips_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
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static struct mtmips_pmx_func mdio_grp[] = {
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FUNC("mdio", MT7620_GPIO_MODE_MDIO, 22, 2),
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FUNC("refclk", MT7620_GPIO_MODE_MDIO_REFCLK, 22, 2),
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};
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static struct mtmips_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
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static struct mtmips_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
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static struct mtmips_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
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static struct mtmips_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
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static struct mtmips_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
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static struct mtmips_pmx_func pa_grp[] = { FUNC("pa", 0, 18, 4) };
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static struct mtmips_pmx_func uartf_grp[] = {
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FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
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FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
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FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
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FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
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FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
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FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
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FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
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};
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static struct mtmips_pmx_func wdt_grp[] = {
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FUNC("wdt rst", 0, 17, 1),
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FUNC("wdt refclk", 0, 17, 1),
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};
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static struct mtmips_pmx_func pcie_rst_grp[] = {
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FUNC("pcie rst", MT7620_GPIO_MODE_PCIE_RST, 36, 1),
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FUNC("pcie refclk", MT7620_GPIO_MODE_PCIE_REF, 36, 1)
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};
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static struct mtmips_pmx_func nd_sd_grp[] = {
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FUNC("nand", MT7620_GPIO_MODE_NAND, 45, 15),
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FUNC("sd", MT7620_GPIO_MODE_SD, 47, 13)
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};
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static struct mtmips_pmx_group mt7620a_pinmux_data[] = {
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GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
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GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
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MT7620_GPIO_MODE_UART0_SHIFT),
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GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
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GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
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GRP_G("wdt", wdt_grp, MT7620_GPIO_MODE_WDT_MASK,
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MT7620_GPIO_MODE_WDT_GPIO, MT7620_GPIO_MODE_WDT_SHIFT),
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GRP_G("mdio", mdio_grp, MT7620_GPIO_MODE_MDIO_MASK,
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MT7620_GPIO_MODE_MDIO_GPIO, MT7620_GPIO_MODE_MDIO_SHIFT),
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GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
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GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
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GRP_G("pcie", pcie_rst_grp, MT7620_GPIO_MODE_PCIE_MASK,
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MT7620_GPIO_MODE_PCIE_GPIO, MT7620_GPIO_MODE_PCIE_SHIFT),
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GRP_G("nd_sd", nd_sd_grp, MT7620_GPIO_MODE_ND_SD_MASK,
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MT7620_GPIO_MODE_ND_SD_GPIO, MT7620_GPIO_MODE_ND_SD_SHIFT),
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GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
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GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
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GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
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GRP("pa", pa_grp, 1, MT7620_GPIO_MODE_PA),
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{ 0 }
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};
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static int mt7620_pinctrl_probe(struct platform_device *pdev)
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{
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return mtmips_pinctrl_init(pdev, mt7620a_pinmux_data);
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}
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static const struct of_device_id mt7620_pinctrl_match[] = {
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{ .compatible = "ralink,mt7620-pinctrl" },
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{ .compatible = "ralink,rt2880-pinmux" },
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{}
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};
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MODULE_DEVICE_TABLE(of, mt7620_pinctrl_match);
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static struct platform_driver mt7620_pinctrl_driver = {
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.probe = mt7620_pinctrl_probe,
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.driver = {
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.name = "mt7620-pinctrl",
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.of_match_table = mt7620_pinctrl_match,
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},
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};
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static int __init mt7620_pinctrl_init(void)
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{
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return platform_driver_register(&mt7620_pinctrl_driver);
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}
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core_initcall_sync(mt7620_pinctrl_init);
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