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7627dc802a
Provide a standard get_irqnr_preamble assembler macro for platforms to use, which retrieves the base address of the GIC CPU interface from gic_cpu_base_addr. Allow platforms to override this by defining HAVE_GET_IRQNR_PREAMBLE. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
57 lines
1.4 KiB
ArmAsm
57 lines
1.4 KiB
ArmAsm
/* arch/arm/mach-tegra/include/mach/entry-macro.S
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*
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* Copyright (C) 2009 Palm, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <mach/iomap.h>
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#include <mach/io.h>
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#if defined(CONFIG_ARM_GIC)
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#define HAVE_GET_IRQNR_PREAMBLE
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#include <asm/hardware/entry-macro-gic.S>
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/* Uses the GIC interrupt controller built into the cpu */
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#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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movw \base, #(ICTRL_BASE & 0x0000ffff)
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movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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#else
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/* legacy interrupt controller for AP16 */
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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@ enable imprecise aborts
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cpsie a
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@ EVP base at 0xf010f000
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mov \base, #0xf0000000
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orr \base, #0x00100000
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orr \base, #0x0000f000
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqnr, [\base, #0x20] @ EVT_IRQ_STS
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cmp \irqnr, #0x80
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.endm
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#endif
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