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c471245bd9
For some of the Qualcomm SoC's, it is possible that some of the fuse regions or entire qfprom region is protected from non-secure access. In such situations, the OS will have to use secure calls to read the region. With that motivation, add secure qfprom driver. Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Link: https://lore.kernel.org/r/20230823132744.350618-18-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
97 lines
2.1 KiB
C
97 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/firmware/qcom/qcom_scm.h>
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#include <linux/mod_devicetable.h>
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#include <linux/nvmem-provider.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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/**
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* struct sec_qfprom - structure holding secure qfprom attributes
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*
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* @base: starting physical address for secure qfprom corrected address space.
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* @dev: qfprom device structure.
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*/
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struct sec_qfprom {
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phys_addr_t base;
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struct device *dev;
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};
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static int sec_qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes)
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{
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struct sec_qfprom *priv = context;
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unsigned int i;
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u8 *val = _val;
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u32 read_val;
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u8 *tmp;
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for (i = 0; i < bytes; i++, reg++) {
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if (i == 0 || reg % 4 == 0) {
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if (qcom_scm_io_readl(priv->base + (reg & ~3), &read_val)) {
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dev_err(priv->dev, "Couldn't access fuse register\n");
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return -EINVAL;
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}
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tmp = (u8 *)&read_val;
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}
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val[i] = tmp[reg & 3];
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}
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return 0;
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}
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static int sec_qfprom_probe(struct platform_device *pdev)
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{
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struct nvmem_config econfig = {
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.name = "sec-qfprom",
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.stride = 1,
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.word_size = 1,
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.id = NVMEM_DEVID_AUTO,
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.reg_read = sec_qfprom_reg_read,
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};
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struct device *dev = &pdev->dev;
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struct nvmem_device *nvmem;
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struct sec_qfprom *priv;
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struct resource *res;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -EINVAL;
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priv->base = res->start;
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econfig.size = resource_size(res);
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econfig.dev = dev;
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econfig.priv = priv;
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priv->dev = dev;
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nvmem = devm_nvmem_register(dev, &econfig);
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return PTR_ERR_OR_ZERO(nvmem);
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}
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static const struct of_device_id sec_qfprom_of_match[] = {
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{ .compatible = "qcom,sec-qfprom" },
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{/* sentinel */},
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};
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MODULE_DEVICE_TABLE(of, sec_qfprom_of_match);
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static struct platform_driver qfprom_driver = {
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.probe = sec_qfprom_probe,
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.driver = {
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.name = "qcom_sec_qfprom",
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.of_match_table = sec_qfprom_of_match,
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},
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};
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module_platform_driver(qfprom_driver);
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MODULE_DESCRIPTION("Qualcomm Secure QFPROM driver");
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MODULE_LICENSE("GPL");
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