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-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYUt1vAAoJEFmIoMA60/r8abgP/3R+5Lsk5/kfAHk5/2Mtqbvg mZ0eDUpY9GbUeMjSq84Nr2H8u7d+1AJCCu8KtDJYZCmjZpnSp2SuE2PS5JoGC7zC fintD24jlIF4/J5+HeVXXmbfr3xATxvpTuiSLEi8sLBRJ3KRIswhMSwoPwOyeTQw v/EclWKPGYcI5Zp0oigY9/Jd3q3lQ17KXppi/0dDoLh7PNOFvEHItXWzmf++u/NP iYT9R1xmzEsy0/HRd6hiwPT2xA8YsAXxgobhHooUgh1FWmZ02Tg1WjgDemOW4lVh kNIUcsLczh7wZCceogrrJ+pwb9+NyyIyKuHPv6OG3ieyz1IZdznaj1fAE5HJYiPo eVS7cP1S6DyV3Y5qFj5F2dSRS7T4GXdXG5mNhmeCpUHs0vfzSCG36jLmhTy8UIxs 1rCf5oFa+uU9q0okfH8VtcGOXqWjGgyxTSGGfF71HUMLnPbsci2fxC2cO6svzIX7 wDY0uxOzpyMIYMuQR6iz7VqvAwEaZ+7pfMIrWWdDcQ9/5tCNJ49cLuKaThPL4bVu juiGBQtnTLg8tjrhjDL9tQiJpuVIweVXyyQ1fvZoVXkMLlhVCF2ttirvwFUit2PB 84OlevQZ+9QdE/qalrWbv4qzhesuiwu0avkzjGoqg6tWTF0epu2AHI2vqy6UBYEG tcfJPEcz1019PKZNSvWy =ut0k -----END PGP SIGNATURE----- Merge tag 'pci-v4.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "PCI changes: - add support for PCI on ARM64 boxes with ACPI. We already had this for theoretical spec-compliant hardware; now we're adding quirks for the actual hardware (Cavium, HiSilicon, Qualcomm, X-Gene) - add runtime PM support for hotplug ports - enable runtime suspend for Intel UHCI that uses platform-specific wakeup signaling - add yet another host bridge registration interface. We hope this is extensible enough to subsume the others - expose device revision in sysfs for DRM - to avoid device conflicts, make sure any VF BAR updates are done before enabling the VF - avoid unnecessary link retrains for ASPM - allow INTx masking on Mellanox devices that support it - allow access to non-standard VPD for Chelsio devices - update Broadcom iProc support for PAXB v2, PAXC v2, inbound DMA, etc - update Rockchip support for max-link-speed - add NVIDIA Tegra210 support - add Layerscape LS1046a support - update R-Car compatibility strings - add Qualcomm MSM8996 support - remove some uninformative bootup messages" * tag 'pci-v4.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (115 commits) PCI: Enable access to non-standard VPD for Chelsio devices (cxgb3) PCI: Expand "VPD access disabled" quirk message PCI: pciehp: Remove loading message PCI: hotplug: Remove hotplug core message PCI: Remove service driver load/unload messages PCI/AER: Log AER IRQ when claiming Root Port PCI/AER: Log errors with PCI device, not PCIe service device PCI/AER: Remove unused version macros PCI/PME: Log PME IRQ when claiming Root Port PCI/PME: Drop unused support for PMEs from Root Complex Event Collectors PCI: Move config space size macros to pci_regs.h x86/platform/intel-mid: Constify mid_pci_platform_pm PCI/ASPM: Don't retrain link if ASPM not possible PCI: iproc: Skip check for legacy IRQ on PAXC buses PCI: pciehp: Leave power indicator on when enabling already-enabled slot PCI: pciehp: Prioritize data-link event over presence detect PCI: rcar: Add gen3 fallback compatibility string for pcie-rcar PCI: rcar: Use gen2 fallback compatibility last PCI: rcar-gen2: Use gen2 fallback compatibility last PCI: rockchip: Move the deassert of pm/aclk/pclk after phy_init() ..
89 lines
1.9 KiB
C
89 lines
1.9 KiB
C
/*
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* Intel MID platform PM support
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*
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* Copyright (C) 2016, Intel Corporation
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*
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/cpu_device_id.h>
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#include <asm/intel-family.h>
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#include <asm/intel-mid.h>
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#include "pci.h"
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static bool mid_pci_power_manageable(struct pci_dev *dev)
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{
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return true;
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}
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static int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
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{
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return intel_mid_pci_set_power_state(pdev, state);
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}
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static pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
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{
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return intel_mid_pci_get_power_state(pdev);
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}
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static pci_power_t mid_pci_choose_state(struct pci_dev *pdev)
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{
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return PCI_D3hot;
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}
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static int mid_pci_sleep_wake(struct pci_dev *dev, bool enable)
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{
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return 0;
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}
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static int mid_pci_run_wake(struct pci_dev *dev, bool enable)
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{
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return 0;
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}
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static bool mid_pci_need_resume(struct pci_dev *dev)
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{
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return false;
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}
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static const struct pci_platform_pm_ops mid_pci_platform_pm = {
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.is_manageable = mid_pci_power_manageable,
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.set_state = mid_pci_set_power_state,
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.get_state = mid_pci_get_power_state,
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.choose_state = mid_pci_choose_state,
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.sleep_wake = mid_pci_sleep_wake,
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.run_wake = mid_pci_run_wake,
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.need_resume = mid_pci_need_resume,
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};
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#define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
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/*
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* This table should be in sync with the one in
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* arch/x86/platform/intel-mid/pwr.c.
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*/
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static const struct x86_cpu_id lpss_cpu_ids[] = {
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ICPU(INTEL_FAM6_ATOM_PENWELL),
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ICPU(INTEL_FAM6_ATOM_MERRIFIELD),
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{}
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};
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static int __init mid_pci_init(void)
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{
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const struct x86_cpu_id *id;
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id = x86_match_cpu(lpss_cpu_ids);
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if (id)
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pci_set_platform_pm(&mid_pci_platform_pm);
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return 0;
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}
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arch_initcall(mid_pci_init);
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