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da52a55cff
Add code enabling the VBI registers for variants of the em28xx chip that support VBI, and make sure the isoc streaming code continues to work for the video component of the stream (note the video and vbi data arrive intermixed on the same isoc pipe). Note that this version just drops the actual VBI data onto the floor as opposed to processing it. The "#ifdef 0" tags are for the videobuf code that appears in the next patch in this series. We created a separate version of the isoc_copy version for parsing the version of the stream that includes VBI data. In theory, they might be able to be merged at some point in the future, but the initial goal is to ensure that we do not cause any regressions with devices that do not have VBI support. This work was sponsored by EyeMagnet Limited. Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
268 lines
8.1 KiB
C
268 lines
8.1 KiB
C
#define EM_GPIO_0 (1 << 0)
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#define EM_GPIO_1 (1 << 1)
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#define EM_GPIO_2 (1 << 2)
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#define EM_GPIO_3 (1 << 3)
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#define EM_GPIO_4 (1 << 4)
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#define EM_GPIO_5 (1 << 5)
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#define EM_GPIO_6 (1 << 6)
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#define EM_GPIO_7 (1 << 7)
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#define EM_GPO_0 (1 << 0)
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#define EM_GPO_1 (1 << 1)
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#define EM_GPO_2 (1 << 2)
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#define EM_GPO_3 (1 << 3)
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/* em2800 registers */
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#define EM2800_R08_AUDIOSRC 0x08
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/* em28xx registers */
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#define EM28XX_R00_CHIPCFG 0x00
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/* em28xx Chip Configuration 0x00 */
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#define EM28XX_CHIPCFG_VENDOR_AUDIO 0x80
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#define EM28XX_CHIPCFG_I2S_VOLUME_CAPABLE 0x40
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#define EM28XX_CHIPCFG_I2S_5_SAMPRATES 0x30
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#define EM28XX_CHIPCFG_I2S_3_SAMPRATES 0x20
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#define EM28XX_CHIPCFG_AC97 0x10
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#define EM28XX_CHIPCFG_AUDIOMASK 0x30
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#define EM28XX_R01_CHIPCFG2 0x01
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/* em28xx Chip Configuration 2 0x01 */
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#define EM28XX_CHIPCFG2_TS_PRESENT 0x10
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#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_MASK 0x0c /* bits 3-2 */
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#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_1MF 0x00
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#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_2MF 0x04
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#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_4MF 0x08
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#define EM28XX_CHIPCFG2_TS_REQ_INTERVAL_8MF 0x0c
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#define EM28XX_CHIPCFG2_TS_PACKETSIZE_MASK 0x03 /* bits 0-1 */
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#define EM28XX_CHIPCFG2_TS_PACKETSIZE_188 0x00
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#define EM28XX_CHIPCFG2_TS_PACKETSIZE_376 0x01
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#define EM28XX_CHIPCFG2_TS_PACKETSIZE_564 0x02
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#define EM28XX_CHIPCFG2_TS_PACKETSIZE_752 0x03
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/* GPIO/GPO registers */
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#define EM2880_R04_GPO 0x04 /* em2880-em2883 only */
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#define EM28XX_R08_GPIO 0x08 /* em2820 or upper */
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#define EM28XX_R06_I2C_CLK 0x06
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/* em28xx I2C Clock Register (0x06) */
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#define EM28XX_I2C_CLK_ACK_LAST_READ 0x80
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#define EM28XX_I2C_CLK_WAIT_ENABLE 0x40
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#define EM28XX_I2C_EEPROM_ON_BOARD 0x08
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#define EM28XX_I2C_EEPROM_KEY_VALID 0x04
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#define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */
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#define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */
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#define EM28XX_I2C_FREQ_25_KHZ 0x02
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#define EM28XX_I2C_FREQ_400_KHZ 0x01
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#define EM28XX_I2C_FREQ_100_KHZ 0x00
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#define EM28XX_R0A_CHIPID 0x0a
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#define EM28XX_R0C_USBSUSP 0x0c /* */
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#define EM28XX_R0E_AUDIOSRC 0x0e
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#define EM28XX_R0F_XCLK 0x0f
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/* em28xx XCLK Register (0x0f) */
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#define EM28XX_XCLK_AUDIO_UNMUTE 0x80 /* otherwise audio muted */
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#define EM28XX_XCLK_I2S_MSB_TIMING 0x40 /* otherwise standard timing */
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#define EM28XX_XCLK_IR_RC5_MODE 0x20 /* otherwise NEC mode */
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#define EM28XX_XCLK_IR_NEC_CHK_PARITY 0x10
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#define EM28XX_XCLK_FREQUENCY_30MHZ 0x00 /* Freq. select (bits [3-0]) */
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#define EM28XX_XCLK_FREQUENCY_15MHZ 0x01
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#define EM28XX_XCLK_FREQUENCY_10MHZ 0x02
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#define EM28XX_XCLK_FREQUENCY_7_5MHZ 0x03
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#define EM28XX_XCLK_FREQUENCY_6MHZ 0x04
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#define EM28XX_XCLK_FREQUENCY_5MHZ 0x05
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#define EM28XX_XCLK_FREQUENCY_4_3MHZ 0x06
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#define EM28XX_XCLK_FREQUENCY_12MHZ 0x07
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#define EM28XX_XCLK_FREQUENCY_20MHZ 0x08
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#define EM28XX_XCLK_FREQUENCY_20MHZ_2 0x09
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#define EM28XX_XCLK_FREQUENCY_48MHZ 0x0a
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#define EM28XX_XCLK_FREQUENCY_24MHZ 0x0b
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#define EM28XX_R10_VINMODE 0x10
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#define EM28XX_R11_VINCTRL 0x11
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/* em28xx Video Input Control Register 0x11 */
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#define EM28XX_VINCTRL_VBI_SLICED 0x80
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#define EM28XX_VINCTRL_VBI_RAW 0x40
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#define EM28XX_VINCTRL_VOUT_MODE_IN 0x20 /* HREF,VREF,VACT in output */
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#define EM28XX_VINCTRL_CCIR656_ENABLE 0x10
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#define EM28XX_VINCTRL_VBI_16BIT_RAW 0x08 /* otherwise 8-bit raw */
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#define EM28XX_VINCTRL_FID_ON_HREF 0x04
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#define EM28XX_VINCTRL_DUAL_EDGE_STROBE 0x02
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#define EM28XX_VINCTRL_INTERLACED 0x01
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#define EM28XX_R12_VINENABLE 0x12 /* */
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#define EM28XX_R14_GAMMA 0x14
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#define EM28XX_R15_RGAIN 0x15
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#define EM28XX_R16_GGAIN 0x16
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#define EM28XX_R17_BGAIN 0x17
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#define EM28XX_R18_ROFFSET 0x18
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#define EM28XX_R19_GOFFSET 0x19
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#define EM28XX_R1A_BOFFSET 0x1a
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#define EM28XX_R1B_OFLOW 0x1b
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#define EM28XX_R1C_HSTART 0x1c
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#define EM28XX_R1D_VSTART 0x1d
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#define EM28XX_R1E_CWIDTH 0x1e
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#define EM28XX_R1F_CHEIGHT 0x1f
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#define EM28XX_R20_YGAIN 0x20
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#define EM28XX_R21_YOFFSET 0x21
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#define EM28XX_R22_UVGAIN 0x22
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#define EM28XX_R23_UOFFSET 0x23
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#define EM28XX_R24_VOFFSET 0x24
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#define EM28XX_R25_SHARPNESS 0x25
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#define EM28XX_R26_COMPR 0x26
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#define EM28XX_R27_OUTFMT 0x27
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/* em28xx Output Format Register (0x27) */
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#define EM28XX_OUTFMT_RGB_8_RGRG 0x00
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#define EM28XX_OUTFMT_RGB_8_GRGR 0x01
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#define EM28XX_OUTFMT_RGB_8_GBGB 0x02
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#define EM28XX_OUTFMT_RGB_8_BGBG 0x03
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#define EM28XX_OUTFMT_RGB_16_656 0x04
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#define EM28XX_OUTFMT_RGB_8_BAYER 0x08 /* Pattern in Reg 0x10[1-0] */
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#define EM28XX_OUTFMT_YUV211 0x10
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#define EM28XX_OUTFMT_YUV422_Y0UY1V 0x14
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#define EM28XX_OUTFMT_YUV422_Y1UY0V 0x15
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#define EM28XX_OUTFMT_YUV411 0x18
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#define EM28XX_R28_XMIN 0x28
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#define EM28XX_R29_XMAX 0x29
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#define EM28XX_R2A_YMIN 0x2a
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#define EM28XX_R2B_YMAX 0x2b
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#define EM28XX_R30_HSCALELOW 0x30
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#define EM28XX_R31_HSCALEHIGH 0x31
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#define EM28XX_R32_VSCALELOW 0x32
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#define EM28XX_R33_VSCALEHIGH 0x33
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#define EM28XX_R34_VBI_START_H 0x34
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#define EM28XX_R35_VBI_START_V 0x35
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#define EM28XX_R36_VBI_WIDTH 0x36
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#define EM28XX_R37_VBI_HEIGHT 0x37
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#define EM28XX_R40_AC97LSB 0x40
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#define EM28XX_R41_AC97MSB 0x41
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#define EM28XX_R42_AC97ADDR 0x42
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#define EM28XX_R43_AC97BUSY 0x43
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#define EM28XX_R45_IR 0x45
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/* 0x45 bit 7 - parity bit
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bits 6-0 - count
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0x46 IR brand
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0x47 IR data
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*/
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/* em2874 registers */
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#define EM2874_R50_IR_CONFIG 0x50
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#define EM2874_R51_IR 0x51
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#define EM2874_R5F_TS_ENABLE 0x5f
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#define EM2874_R80_GPIO 0x80
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/* em2874 IR config register (0x50) */
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#define EM2874_IR_NEC 0x00
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#define EM2874_IR_RC5 0x04
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#define EM2874_IR_RC5_MODE_0 0x08
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#define EM2874_IR_RC5_MODE_6A 0x0b
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/* em2874 Transport Stream Enable Register (0x5f) */
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#define EM2874_TS1_CAPTURE_ENABLE (1 << 0)
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#define EM2874_TS1_FILTER_ENABLE (1 << 1)
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#define EM2874_TS1_NULL_DISCARD (1 << 2)
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#define EM2874_TS2_CAPTURE_ENABLE (1 << 4)
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#define EM2874_TS2_FILTER_ENABLE (1 << 5)
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#define EM2874_TS2_NULL_DISCARD (1 << 6)
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/* register settings */
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#define EM2800_AUDIO_SRC_TUNER 0x0d
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#define EM2800_AUDIO_SRC_LINE 0x0c
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#define EM28XX_AUDIO_SRC_TUNER 0xc0
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#define EM28XX_AUDIO_SRC_LINE 0x80
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/* FIXME: Need to be populated with the other chip ID's */
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enum em28xx_chip_id {
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CHIP_ID_EM2710 = 17,
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CHIP_ID_EM2820 = 18, /* Also used by some em2710 */
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CHIP_ID_EM2840 = 20,
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CHIP_ID_EM2750 = 33,
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CHIP_ID_EM2860 = 34,
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CHIP_ID_EM2870 = 35,
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CHIP_ID_EM2883 = 36,
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CHIP_ID_EM2874 = 65,
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};
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/*
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* Registers used by em202 and other AC97 chips
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*/
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/* Standard AC97 registers */
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#define AC97_RESET 0x00
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/* Output volumes */
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#define AC97_MASTER_VOL 0x02
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#define AC97_LINE_LEVEL_VOL 0x04 /* Some devices use for headphones */
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#define AC97_MASTER_MONO_VOL 0x06
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/* Input volumes */
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#define AC97_PC_BEEP_VOL 0x0a
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#define AC97_PHONE_VOL 0x0c
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#define AC97_MIC_VOL 0x0e
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#define AC97_LINEIN_VOL 0x10
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#define AC97_CD_VOL 0x12
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#define AC97_VIDEO_VOL 0x14
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#define AC97_AUX_VOL 0x16
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#define AC97_PCM_OUT_VOL 0x18
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/* capture registers */
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#define AC97_RECORD_SELECT 0x1a
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#define AC97_RECORD_GAIN 0x1c
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/* control registers */
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#define AC97_GENERAL_PURPOSE 0x20
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#define AC97_3D_CTRL 0x22
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#define AC97_AUD_INT_AND_PAG 0x24
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#define AC97_POWER_DOWN_CTRL 0x26
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#define AC97_EXT_AUD_ID 0x28
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#define AC97_EXT_AUD_CTRL 0x2a
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/* Supported rate varies for each AC97 device
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if write an unsupported value, it will return the closest one
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*/
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#define AC97_PCM_OUT_FRONT_SRATE 0x2c
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#define AC97_PCM_OUT_SURR_SRATE 0x2e
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#define AC97_PCM_OUT_LFE_SRATE 0x30
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#define AC97_PCM_IN_SRATE 0x32
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/* For devices with more than 2 channels, extra output volumes */
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#define AC97_LFE_MASTER_VOL 0x36
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#define AC97_SURR_MASTER_VOL 0x38
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/* Digital SPDIF output control */
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#define AC97_SPDIF_OUT_CTRL 0x3a
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/* Vendor ID identifier */
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#define AC97_VENDOR_ID1 0x7c
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#define AC97_VENDOR_ID2 0x7e
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/* EMP202 vendor registers */
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#define EM202_EXT_MODEM_CTRL 0x3e
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#define EM202_GPIO_CONF 0x4c
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#define EM202_GPIO_POLARITY 0x4e
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#define EM202_GPIO_STICKY 0x50
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#define EM202_GPIO_MASK 0x52
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#define EM202_GPIO_STATUS 0x54
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#define EM202_SPDIF_OUT_SEL 0x6a
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#define EM202_ANTIPOP 0x72
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#define EM202_EAPD_GPIO_ACCESS 0x74
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