Ilpo Järvinen 6052a005ca mfd: intel-m10-bmc: Support multiple CSR register layouts ... There are different addresses for the MAX10 CSR registers. Introducing a new data structure m10bmc_csr_map for the register definition of MAX10 CSR. Provide the csr_map for SPI. Co-developed-by: Tianfei zhang <tianfei.zhang@intel.com> Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> Reviewed-by: Russ Weight <russell.h.weight@intel.com> Reviewed-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Lee Jones <lee@kernel.org> Link: https://lore.kernel.org/r/20230116100845.6153-6-ilpo.jarvinen@linux.intel.com		2023-01-27 10:36:29 +00:00
..
altera-cvp.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
altera-fpga2sdram.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
altera-freeze-bridge.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
altera-hps2fpga.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
altera-pr-ip-core-plat.c	fpga: fpga-mgr: altera-pr-ip: Simplify registration	2020-12-01 18:49:32 +01:00
altera-pr-ip-core.c	fpga: altera-pr-ip: fix unsigned comparison with less than zero	2022-06-10 15:48:23 +08:00
altera-ps-spi.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
dfl-afu-dma-region.c
dfl-afu-error.c	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-afu-main.c	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-afu-region.c
dfl-afu.h	fpga: dfl: afu: harden port enable logic	2021-03-24 11:15:04 -07:00
dfl-fme-br.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
dfl-fme-error.c
dfl-fme-main.c
dfl-fme-mgr.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
dfl-fme-perf.c	fpga: dfl: fme: Fix cpu hotplug issue in performance reporting	2021-07-27 11:05:16 -07:00
dfl-fme-pr.c	fpga: fix spelling mistakes	2021-07-21 19:54:21 -07:00
dfl-fme-pr.h
dfl-fme-region.c	fpga: region: Use standard dev_release for class driver	2021-11-28 14:02:41 -08:00
dfl-fme.h
dfl-n3000-nios.c	fpga: fix spelling mistakes	2021-07-21 19:54:21 -07:00
dfl-pci.c	fpga: dfl-pci: Add IDs for Intel N6000, N6001 and C6100 cards	2022-08-15 11:38:31 +08:00
dfl.c	fpga: prevent integer overflow in dfl_feature_ioctl_set_irq()	2022-09-04 01:48:00 +08:00
dfl.h	fpga: dfl: Allow Port to be linked to FME's DFL	2022-05-10 16:05:38 +08:00
fpga-bridge.c	fpga: Directly use ida_alloc()/free()	2022-06-08 17:04:39 +08:00
fpga-mgr.c	fpga: fpga-mgr: Fix spelling mistake "bitsream" -> "bitstream"	2022-06-29 15:18:18 +08:00
fpga-region.c	fpga: Directly use ida_alloc()/free()	2022-06-08 17:04:39 +08:00
ice40-spi.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
intel-m10-bmc-sec-update.c	mfd: intel-m10-bmc: Support multiple CSR register layouts	2023-01-27 10:36:29 +00:00
Kconfig	mfd: intel-m10-bmc: Split into core and spi specific parts	2023-01-27 10:35:00 +00:00
lattice-sysconfig-spi.c	fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager	2022-10-25 14:44:03 +08:00
lattice-sysconfig.c	fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager	2022-10-25 14:44:03 +08:00
lattice-sysconfig.h	fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager	2022-10-25 14:44:03 +08:00
machxo2-spi.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
Makefile	fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager	2022-10-25 14:44:03 +08:00
microchip-spi.c	fpga: microchip-spi: add missing module author entry	2022-08-15 11:38:57 +08:00
of-fpga-region.c	fpga: fpga-region: fix kernel-doc formatting issues	2022-05-10 16:05:00 +08:00
socfpga-a10.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
socfpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
stratix10-soc.c	fpga: stratix10-soc: Do not use ret uninitialized in s10_probe()	2021-12-02 20:07:17 -08:00
ts73xx-fpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
versal-fpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
xilinx-pr-decoupler.c	fpga: bridge: Use standard dev_release for class driver	2021-11-28 14:02:13 -08:00
xilinx-spi.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00
zynq-fpga.c	fpga: zynq: Switch to use dev_err_probe() helper	2022-10-25 14:25:02 +08:00
zynqmp-fpga.c	fpga: mgr: Use standard dev_release for class driver	2021-11-28 13:59:13 -08:00