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Document RZ/G1 and RZ/G2 support. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
31 lines
1.0 KiB
Plaintext
31 lines
1.0 KiB
Plaintext
* Renesas VSP Video Processing Engine
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The VSP is a video processing engine that supports up-/down-scaling, alpha
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blending, color space conversion and various other image processing features.
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It can be found in the Renesas R-Car Gen2, R-Car Gen3, RZ/G1, and RZ/G2 SoCs.
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Required properties:
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- compatible: Must contain one of the following values
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- "renesas,vsp1" for the R-Car Gen2 and RZ/G1 VSP1
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- "renesas,vsp2" for the R-Car Gen3 and RZ/G2 VSP2
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- reg: Base address and length of the registers block for the VSP.
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- interrupts: VSP interrupt specifier.
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- clocks: A phandle + clock-specifier pair for the VSP functional clock.
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Optional properties:
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- renesas,fcp: A phandle referencing the FCP that handles memory accesses
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for the VSP. Not needed on Gen2, mandatory on Gen3.
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Example: R8A7790 (R-Car H2) VSP1-S node
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vsp@fe928000 {
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compatible = "renesas,vsp1";
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reg = <0 0xfe928000 0 0x8000>;
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interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
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};
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