Tomasz Figa 5fadfc7ed3 clk: samsung: exynos4: Register PLL rate tables for Exynos4210 ... This patch adds rate tables for PLLs that can be reconfigured at runtime for Exynos4210 SoCs. Provided tables contain PLL coefficients for input clock of 24 MHz and so are registered only in this case. MPLL does not need runtime reconfiguration and so table for it is not provided. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>		2013-09-06 13:33:57 -07:00
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clk-exynos4.c	clk: samsung: exynos4: Register PLL rate tables for Exynos4210	2013-09-06 13:33:57 -07:00
clk-exynos5250.c	clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem	2013-08-28 19:23:40 -07:00
clk-exynos5420.c	clk/exynos5420: assign dout_pixel id to pixel clock divider	2013-08-29 17:48:12 -07:00
clk-exynos5440.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk-exynos-audss.c	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
clk-pll.c	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-pll.h	clk: samsung: pll: Add support for rate configuration of PLL46xx	2013-09-06 13:33:47 -07:00
clk-s3c64xx.c	clk: s3c64xx: Fix incorrect placement of __initdata	2013-08-27 18:36:20 -07:00
clk.c	clk: samsung: Modify _get_rate() helper to use __clk_lookup()	2013-09-06 13:33:15 -07:00
clk.h	clk: add CLK_SET_RATE_NO_REPARENT flag	2013-08-19 12:27:17 -07:00
Makefile	clk: samsung: Add clock driver for S3C64xx SoCs	2013-08-05 11:58:37 -07:00