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476276d69d
Document the device tree binding for Broadcom iProc architecture based clock controller Signed-off-by: Ray Jui <rjui@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
133 lines
4.5 KiB
Plaintext
133 lines
4.5 KiB
Plaintext
Broadcom iProc Family Clocks
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The iProc clock controller manages clocks that are common to the iProc family.
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An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
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LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
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comprises of several leaf clocks
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Required properties for a PLL and its leaf clocks:
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- compatible:
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Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
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Cygnus has a compatible string of "brcm,cygnus-genpll"
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- #clock-cells:
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Have a value of <1> since there are more than 1 leaf clock of a given PLL
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- reg:
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Define the base and range of the I/O address space that contain the iProc
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clock control registers required for the PLL
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- clocks:
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The input parent clock phandle for the PLL. For most iProc PLLs, this is an
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onboard crystal with a fixed rate
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- clock-output-names:
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An ordered list of strings defining the names of the clocks
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Example:
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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genpll: genpll {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-genpll";
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reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
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"enet_sw", "audio_125", "can";
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};
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Required properties for ASIU clocks:
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ASIU clocks are a special case. These clocks are derived directly from the
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reference clock of the onboard crystal
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- compatible:
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Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
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clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
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- #clock-cells:
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Have a value of <1> since there are more than 1 ASIU clocks
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- reg:
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Define the base and range of the I/O address space that contain the iProc
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clock control registers required for ASIU clocks
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- clocks:
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The input parent clock phandle for the ASIU clock, i.e., the onboard
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crystal
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- clock-output-names:
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An ordered list of strings defining the names of the ASIU clocks
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Example:
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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asiu_clks: asiu_clks {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-asiu-clk";
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reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
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clocks = <&osc>;
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clock-output-names = "keypad", "adc/touch", "pwm";
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};
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Cygnus
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------
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PLL and leaf clock compatible strings for Cygnus are:
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"brcm,cygnus-armpll"
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"brcm,cygnus-genpll"
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"brcm,cygnus-lcpll0"
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"brcm,cygnus-mipipll"
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"brcm,cygnus-asiu-clk"
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The following table defines the set of PLL/clock index and ID for Cygnus.
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These clock IDs are defined in:
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"include/dt-bindings/clock/bcm-cygnus.h"
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Clock Source (Parent) Index ID
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--- ----- ----- ---------
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crystal N/A N/A N/A
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armpll crystal N/A N/A
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keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
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adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
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pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
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genpll crystal 0 BCM_CYGNUS_GENPLL
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axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
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250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
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ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
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enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
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audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
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can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
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lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
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pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
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ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
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sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
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usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
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smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
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ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
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mipipll crystal 0 BCM_CYGNUS_MIPIPLL
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ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
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ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
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ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
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ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
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ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
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ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
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