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e37b0c9670
Convert core 8xx drivers to use in_xxxbe/in_xxx macros instead of direct memory references. Other than making IO accesses explicit (which is a plus for readability), a common set of macros provides a unified place for the volatile flag to constraint compiler code reordering. There are several unlucky places at the moment which lack the volatile flag. Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/interrupt.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/8xx_immap.h>
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#include <asm/mpc8xx.h>
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#include "ppc8xx_pic.h"
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extern int cpm_get_irq(struct pt_regs *regs);
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/* The 8xx internal interrupt controller. It is usually
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* the only interrupt controller. Some boards, like the MBX and
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* Sandpoint have the 8259 as a secondary controller. Depending
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* upon the processor type, the internal controller can have as
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* few as 16 interrups or as many as 64. We could use the
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* "clear_bit()" and "set_bit()" functions like other platforms,
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* but they are overkill for us.
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*/
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static void m8xx_mask_irq(unsigned int irq_nr)
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{
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int bit, word;
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
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out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
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}
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static void m8xx_unmask_irq(unsigned int irq_nr)
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{
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int bit, word;
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] |= (1 << (31-bit));
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out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
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}
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static void m8xx_end_irq(unsigned int irq_nr)
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{
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq_nr].action) {
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int bit, word;
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] |= (1 << (31-bit));
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out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
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}
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}
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static void m8xx_mask_and_ack(unsigned int irq_nr)
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{
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int bit, word;
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bit = irq_nr & 0x1f;
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word = irq_nr >> 5;
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ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
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out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_simask, ppc_cached_irq_mask[word]);
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out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sipend, 1 << (31-bit));
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}
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struct hw_interrupt_type ppc8xx_pic = {
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.typename = " 8xx SIU ",
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.enable = m8xx_unmask_irq,
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.disable = m8xx_mask_irq,
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.ack = m8xx_mask_and_ack,
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.end = m8xx_end_irq,
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};
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/*
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* We either return a valid interrupt or -1 if there is nothing pending
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*/
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int
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m8xx_get_irq(struct pt_regs *regs)
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{
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int irq;
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/* For MPC8xx, read the SIVEC register and shift the bits down
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* to get the irq number.
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*/
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irq = in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_sivec) >> 26;
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/*
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* When we read the sivec without an interrupt to process, we will
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* get back SIU_LEVEL7. In this case, return -1
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*/
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if (irq == CPM_INTERRUPT)
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irq = CPM_IRQ_OFFSET + cpm_get_irq(regs);
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#if defined(CONFIG_PCI)
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else if (irq == ISA_BRIDGE_INT) {
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int isa_irq;
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if ((isa_irq = i8259_poll(regs)) >= 0)
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irq = I8259_IRQ_OFFSET + isa_irq;
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}
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#endif /* CONFIG_PCI */
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else if (irq == SIU_LEVEL7)
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irq = -1;
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return irq;
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}
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#if defined(CONFIG_MBX) && defined(CONFIG_PCI)
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/* Only the MBX uses the external 8259. This allows us to catch standard
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* drivers that may mess up the internal interrupt controllers, and also
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* allow them to run without modification on the MBX.
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*/
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void mbx_i8259_action(int irq, void *dev_id, struct pt_regs *regs)
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{
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/* This interrupt handler never actually gets called. It is
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* installed only to unmask the 8259 cascade interrupt in the SIU
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* and to make the 8259 cascade interrupt visible in /proc/interrupts.
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*/
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}
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#endif /* CONFIG_PCI */
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